#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32 LockOut: 1

UINT32 Enable_PPIN: 1

UINT32 Reserved1: 30

UINT32 Reserved2: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_PPIN_CTL

Definition at line 105 of file XeonPhiMsr.h.

Field Documentation

◆

struct { ... } MSR_XEON_PHI_PPIN_CTL_REGISTER::Bits

Individual bit fields

◆ Enable_PPIN

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::Enable_PPIN

[Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0.

Definition at line 127 of file XeonPhiMsr.h.

◆ LockOut

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::LockOut

[Bit 0] LockOut (R/WO) Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a privileged inventory initialization agent to access MSR_PPIN. After reading MSR_PPIN, the privileged inventory initialization agent should write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and prevent unauthorized modification to MSR_PPIN_CTL.

Definition at line 120 of file XeonPhiMsr.h.

◆ Reserved1

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::Reserved1

Definition at line 128 of file XeonPhiMsr.h.

◆ Reserved2

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::Reserved2

Definition at line 129 of file XeonPhiMsr.h.

◆ Uint32

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 134 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_PPIN_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 138 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h

Data Fields