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Data Fields
MSR_XEON_PHI_SMI_COUNT_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields

struct {
   UINT32   SMICount: 32
 
   UINT32   Reserved: 32
 
} Bits
 
UINT32 Uint32
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_SMI_COUNT

Definition at line 62 of file XeonPhiMsr.h.

Field Documentation

◆ 

struct { ... } MSR_XEON_PHI_SMI_COUNT_REGISTER::Bits

Individual bit fields

◆ Reserved

UINT32 MSR_XEON_PHI_SMI_COUNT_REGISTER::Reserved

Definition at line 71 of file XeonPhiMsr.h.

◆ SMICount

UINT32 MSR_XEON_PHI_SMI_COUNT_REGISTER::SMICount

[Bits 31:0] SMI Count (R/O).

Definition at line 70 of file XeonPhiMsr.h.

◆ Uint32

UINT32 MSR_XEON_PHI_SMI_COUNT_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 76 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_SMI_COUNT_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 80 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file: