#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32 BankSupport: 32

UINT32 Reserved4: 24

UINT32 TargetedSMI: 1

UINT32 SMM_CPU_SVRSTR: 1

UINT32 SMM_Code_Access_Chk: 1

UINT32 Long_Flow_Indication: 1

UINT32 Reserved3: 4

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_SMM_MCA_CAP

Definition at line 481 of file XeonPhiMsr.h.

Field Documentation

◆ BankSupport

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::BankSupport

[Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is set, that bank supports Enhanced MCA (Default all 0; does not support EMCA).

Definition at line 491 of file XeonPhiMsr.h.

◆

struct { ... } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

◆ Long_Flow_Indication

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler.

Definition at line 513 of file XeonPhiMsr.h.

◆ Reserved3

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Reserved3

Definition at line 514 of file XeonPhiMsr.h.

◆ Reserved4

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Reserved4

Definition at line 492 of file XeonPhiMsr.h.

◆ SMM_Code_Access_Chk

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and a host-space interface available to SMM handler.

Definition at line 507 of file XeonPhiMsr.h.

◆ SMM_CPU_SVRSTR

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::SMM_CPU_SVRSTR

[Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature is supported.

Definition at line 501 of file XeonPhiMsr.h.

◆ TargetedSMI

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::TargetedSMI

[Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.

Definition at line 496 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 519 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h

Data Fields