MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32   Reserved1: 16
UINT32   TemperatureTarget: 8
UINT32   TargetOffset: 6
UINT32   Reserved2: 2
UINT32   Reserved3: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_TEMPERATURE_TARGET

Definition at line 636 of file XeonPhiMsr.h.

Field Documentation

struct { ... } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

Reserved1

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Reserved1

Definition at line 641 of file XeonPhiMsr.h.

Reserved2

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Reserved2

Definition at line 650 of file XeonPhiMsr.h.

Reserved3

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Reserved3

Definition at line 651 of file XeonPhiMsr.h.

TargetOffset

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::TargetOffset

[Bits 29:24] Target Offset (R/W).

Definition at line 649 of file XeonPhiMsr.h.

TemperatureTarget

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (R).

Definition at line 645 of file XeonPhiMsr.h.

Uint32

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 656 of file XeonPhiMsr.h.

Uint64

UINT64 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 660 of file XeonPhiMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h