#include <AArch64/AArch64Mmu.h>

Macros
#define	ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ

#define	CPACR_TTA_EN (1UL << 28)

#define	CPACR_FPEN_EL1 (1UL << 20)

#define	CPACR_FPEN_FULL (3UL << 20)

#define	CPACR_DEFAULT CPACR_FPEN_FULL

#define	AARCH64_CPTR_TFP (1 << 10)

#define	AARCH64_CPTR_RES1 0x33ff

#define	AARCH64_CPTR_DEFAULT AARCH64_CPTR_RES1

#define	AARCH64_MMFR1_VH (0xF << 8)

#define	AARCH64_PFR0_FP (0xF << 16)

#define	AARCH64_PFR0_GIC (0xF << 24)

#define	AARCH64_DFR0_TRACEVER (0xFULL << 4)

#define	AARCH64_DFR0_TRBE (0xFULL << 44)

#define	SCR_NS (1 << 0)

#define	SCR_IRQ (1 << 1)

#define	SCR_FIQ (1 << 2)

#define	SCR_EA (1 << 3)

#define	SCR_FW (1 << 4)

#define	SCR_AW (1 << 5)

#define	ARM_CPU_TYPE_SHIFT 4

#define	ARM_CPU_TYPE_MASK 0xFFF

#define	ARM_CPU_TYPE_AEMV8 0xD0F

#define	ARM_CPU_TYPE_A53 0xD03

#define	ARM_CPU_TYPE_A57 0xD07

#define	ARM_CPU_TYPE_A72 0xD08

#define	ARM_CPU_TYPE_A15 0xC0F

#define	ARM_CPU_TYPE_A9 0xC09

#define	ARM_CPU_TYPE_A7 0xC07

#define	ARM_CPU_TYPE_A5 0xC05

#define	ARM_CPU_REV_MASK ((0xF << 20) \| (0xF) )

#define	ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) \| ((pn) & 0xF))

#define	ARM_HCR_FMO BIT3

#define	ARM_HCR_IMO BIT4

#define	ARM_HCR_AMO BIT5

#define	ARM_HCR_TSC BIT19

#define	ARM_HCR_TGE BIT27

#define	AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))

#define	AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))

#define	AARCH64_ESR_EC_SMC32 (0x13 << 26)

#define	AARCH64_ESR_EC_SMC64 (0x17 << 26)

#define	AARCH64_EL3 0xC

#define	AARCH64_EL2 0x8

#define	AARCH64_EL1 0x4

#define	SPSR_A BIT8

#define	SPSR_I BIT7

#define	SPSR_F BIT6

#define	SPSR_AARCH32 BIT4

#define	SPSR_AARCH32_MODE_USER 0x0

#define	SPSR_AARCH32_MODE_FIQ 0x1

#define	SPSR_AARCH32_MODE_IRQ 0x2

#define	SPSR_AARCH32_MODE_SVC 0x3

#define	SPSR_AARCH32_MODE_ABORT 0x7

#define	SPSR_AARCH32_MODE_UNDEF 0xB

#define	SPSR_AARCH32_MODE_SYS 0xF

#define	CNTHCTL_EL2_EL1PCTEN BIT0

#define	CNTHCTL_EL2_EL1PCEN BIT1

#define	ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)

#define	ARM_VECTOR_CUR_SP0_SYNC 0x000

#define	ARM_VECTOR_CUR_SP0_IRQ 0x080

#define	ARM_VECTOR_CUR_SP0_FIQ 0x100

#define	ARM_VECTOR_CUR_SP0_SERR 0x180

#define	ARM_VECTOR_CUR_SPX_SYNC 0x200

#define	ARM_VECTOR_CUR_SPX_IRQ 0x280

#define	ARM_VECTOR_CUR_SPX_FIQ 0x300

#define	ARM_VECTOR_CUR_SPX_SERR 0x380

#define	ARM_VECTOR_LOW_A64_SYNC 0x400

#define	ARM_VECTOR_LOW_A64_IRQ 0x480

#define	ARM_VECTOR_LOW_A64_FIQ 0x500

#define	ARM_VECTOR_LOW_A64_SERR 0x580

#define	ARM_VECTOR_LOW_A32_SYNC 0x600

#define	ARM_VECTOR_LOW_A32_IRQ 0x680

#define	ARM_VECTOR_LOW_A32_FIQ 0x700

#define	ARM_VECTOR_LOW_A32_SERR 0x780

#define	ID_AA64ISAR2_EL1 S3_0_C0_C6_2

#define	ID_AA64MMFR2_EL1 S3_0_C0_C7_2

#define	VECTOR_BASE(tbl)

#define	VECTOR_ENTRY(tbl, off) .org off

#define	VECTOR_END(tbl)

Functions
VOID EFIAPI	ArmEnableSWPInstruction (VOID)

UINTN EFIAPI	ArmReadCbar (VOID)

UINTN EFIAPI	ArmReadTpidrurw (VOID)

VOID EFIAPI	ArmWriteTpidrurw (UINTN Value)

UINTN EFIAPI	ArmGetTCR (VOID)

VOID EFIAPI	ArmSetTCR (UINTN Value)

UINTN EFIAPI	ArmGetMAIR (VOID)

VOID EFIAPI	ArmSetMAIR (UINTN Value)

VOID EFIAPI	ArmDisableAlignmentCheck (VOID)

VOID EFIAPI	ArmEnableAlignmentCheck (VOID)

VOID EFIAPI	ArmDisableStackAlignmentCheck (VOID)

VOID EFIAPI	ArmEnableStackAlignmentCheck (VOID)

VOID EFIAPI	ArmDisableAllExceptions (VOID)

VOID	ArmWriteHcr (IN UINTN Hcr)

UINTN	ArmReadHcr (VOID)

UINTN	ArmReadCurrentEL (VOID)

UINT32	ArmReadCntHctl (VOID)

VOID	ArmWriteCntHctl (IN UINT32 CntHctl)

Detailed Description

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file AArch64.h.

Macro Definition Documentation

◆ AARCH64_CPTR_DEFAULT

#define AARCH64_CPTR_DEFAULT AARCH64_CPTR_RES1

Definition at line 27 of file AArch64.h.

◆ AARCH64_CPTR_RES1

#define AARCH64_CPTR_RES1 0x33ff

Definition at line 26 of file AArch64.h.

◆ AARCH64_CPTR_TFP

#define AARCH64_CPTR_TFP (1 << 10)

Definition at line 25 of file AArch64.h.

◆ AARCH64_DFR0_TRACEVER

#define AARCH64_DFR0_TRACEVER (0xFULL << 4)

Definition at line 37 of file AArch64.h.

◆ AARCH64_DFR0_TRBE

#define AARCH64_DFR0_TRBE (0xFULL << 44)

Definition at line 38 of file AArch64.h.

◆ AARCH64_EL1

#define AARCH64_EL1 0x4

Definition at line 80 of file AArch64.h.

◆ AARCH64_EL2

#define AARCH64_EL2 0x8

Definition at line 79 of file AArch64.h.

◆ AARCH64_EL3

#define AARCH64_EL3 0xC

Definition at line 78 of file AArch64.h.

◆ AARCH64_ESR_EC

#define AARCH64_ESR_EC ( Ecr ) ((0x3F << 26) & (Ecr))

Definition at line 71 of file AArch64.h.

◆ AARCH64_ESR_EC_SMC32

#define AARCH64_ESR_EC_SMC32 (0x13 << 26)

Definition at line 74 of file AArch64.h.

◆ AARCH64_ESR_EC_SMC64

#define AARCH64_ESR_EC_SMC64 (0x17 << 26)

Definition at line 75 of file AArch64.h.

◆ AARCH64_ESR_ISS

#define AARCH64_ESR_ISS ( Ecr ) ((0x1FFFFFF) & (Ecr))

Definition at line 72 of file AArch64.h.

◆ AARCH64_MMFR1_VH

#define AARCH64_MMFR1_VH (0xF << 8)

Definition at line 30 of file AArch64.h.

◆ AARCH64_PFR0_FP

#define AARCH64_PFR0_FP (0xF << 16)

Definition at line 33 of file AArch64.h.

◆ AARCH64_PFR0_GIC

#define AARCH64_PFR0_GIC (0xF << 24)

Definition at line 34 of file AArch64.h.

◆ ARM_ARCH_EXCEPTION_IRQ

#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ

Definition at line 16 of file AArch64.h.

◆ ARM_CPU_REV

#define ARM_CPU_REV	(	rn,
		pn
	)	((((rn) & 0xF) << 20) \| ((pn) & 0xF))

Definition at line 61 of file AArch64.h.

◆ ARM_CPU_REV_MASK

#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )

Definition at line 60 of file AArch64.h.

◆ ARM_CPU_TYPE_A15

#define ARM_CPU_TYPE_A15 0xC0F

Definition at line 55 of file AArch64.h.

◆ ARM_CPU_TYPE_A5

#define ARM_CPU_TYPE_A5 0xC05

Definition at line 58 of file AArch64.h.

◆ ARM_CPU_TYPE_A53

#define ARM_CPU_TYPE_A53 0xD03

Definition at line 52 of file AArch64.h.

◆ ARM_CPU_TYPE_A57

#define ARM_CPU_TYPE_A57 0xD07

Definition at line 53 of file AArch64.h.

◆ ARM_CPU_TYPE_A7

#define ARM_CPU_TYPE_A7 0xC07

Definition at line 57 of file AArch64.h.

◆ ARM_CPU_TYPE_A72

#define ARM_CPU_TYPE_A72 0xD08

Definition at line 54 of file AArch64.h.

◆ ARM_CPU_TYPE_A9

#define ARM_CPU_TYPE_A9 0xC09

Definition at line 56 of file AArch64.h.

◆ ARM_CPU_TYPE_AEMV8

#define ARM_CPU_TYPE_AEMV8 0xD0F

Definition at line 51 of file AArch64.h.

◆ ARM_CPU_TYPE_MASK

#define ARM_CPU_TYPE_MASK 0xFFF

Definition at line 50 of file AArch64.h.

◆ ARM_CPU_TYPE_SHIFT

#define ARM_CPU_TYPE_SHIFT 4

Definition at line 49 of file AArch64.h.

◆ ARM_HCR_AMO

#define ARM_HCR_AMO BIT5

Definition at line 66 of file AArch64.h.

◆ ARM_HCR_FMO

#define ARM_HCR_FMO BIT3

Definition at line 64 of file AArch64.h.

◆ ARM_HCR_IMO

#define ARM_HCR_IMO BIT4

Definition at line 65 of file AArch64.h.

◆ ARM_HCR_TGE

#define ARM_HCR_TGE BIT27

Definition at line 68 of file AArch64.h.

◆ ARM_HCR_TSC

#define ARM_HCR_TSC BIT19

Definition at line 67 of file AArch64.h.

◆ ARM_VECTOR_CUR_SP0_FIQ

#define ARM_VECTOR_CUR_SP0_FIQ 0x100

Definition at line 106 of file AArch64.h.

◆ ARM_VECTOR_CUR_SP0_IRQ

#define ARM_VECTOR_CUR_SP0_IRQ 0x080

Definition at line 105 of file AArch64.h.

◆ ARM_VECTOR_CUR_SP0_SERR

#define ARM_VECTOR_CUR_SP0_SERR 0x180

Definition at line 107 of file AArch64.h.

◆ ARM_VECTOR_CUR_SP0_SYNC

#define ARM_VECTOR_CUR_SP0_SYNC 0x000

Definition at line 104 of file AArch64.h.

◆ ARM_VECTOR_CUR_SPX_FIQ

#define ARM_VECTOR_CUR_SPX_FIQ 0x300

Definition at line 111 of file AArch64.h.

◆ ARM_VECTOR_CUR_SPX_IRQ

#define ARM_VECTOR_CUR_SPX_IRQ 0x280

Definition at line 110 of file AArch64.h.

◆ ARM_VECTOR_CUR_SPX_SERR

#define ARM_VECTOR_CUR_SPX_SERR 0x380

Definition at line 112 of file AArch64.h.

◆ ARM_VECTOR_CUR_SPX_SYNC

#define ARM_VECTOR_CUR_SPX_SYNC 0x200

Definition at line 109 of file AArch64.h.

◆ ARM_VECTOR_LOW_A32_FIQ

#define ARM_VECTOR_LOW_A32_FIQ 0x700

Definition at line 121 of file AArch64.h.

◆ ARM_VECTOR_LOW_A32_IRQ

#define ARM_VECTOR_LOW_A32_IRQ 0x680

Definition at line 120 of file AArch64.h.

◆ ARM_VECTOR_LOW_A32_SERR

#define ARM_VECTOR_LOW_A32_SERR 0x780

Definition at line 122 of file AArch64.h.

◆ ARM_VECTOR_LOW_A32_SYNC

#define ARM_VECTOR_LOW_A32_SYNC 0x600

Definition at line 119 of file AArch64.h.

◆ ARM_VECTOR_LOW_A64_FIQ

#define ARM_VECTOR_LOW_A64_FIQ 0x500

Definition at line 116 of file AArch64.h.

◆ ARM_VECTOR_LOW_A64_IRQ

#define ARM_VECTOR_LOW_A64_IRQ 0x480

Definition at line 115 of file AArch64.h.

◆ ARM_VECTOR_LOW_A64_SERR

#define ARM_VECTOR_LOW_A64_SERR 0x580

Definition at line 117 of file AArch64.h.

◆ ARM_VECTOR_LOW_A64_SYNC

#define ARM_VECTOR_LOW_A64_SYNC 0x400

Definition at line 114 of file AArch64.h.

◆ ARM_VECTOR_TABLE_ALIGNMENT

#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)

Definition at line 101 of file AArch64.h.

◆ CNTHCTL_EL2_EL1PCEN

#define CNTHCTL_EL2_EL1PCEN BIT1

Definition at line 99 of file AArch64.h.

◆ CNTHCTL_EL2_EL1PCTEN

#define CNTHCTL_EL2_EL1PCTEN BIT0

Definition at line 98 of file AArch64.h.

◆ CPACR_DEFAULT

#define CPACR_DEFAULT CPACR_FPEN_FULL

Definition at line 22 of file AArch64.h.

◆ CPACR_FPEN_EL1

#define CPACR_FPEN_EL1 (1UL << 20)

Definition at line 20 of file AArch64.h.

◆ CPACR_FPEN_FULL

#define CPACR_FPEN_FULL (3UL << 20)

Definition at line 21 of file AArch64.h.

◆ CPACR_TTA_EN

#define CPACR_TTA_EN (1UL << 28)

Definition at line 19 of file AArch64.h.

◆ ID_AA64ISAR2_EL1

#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2

Definition at line 126 of file AArch64.h.

◆ ID_AA64MMFR2_EL1

#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2

Definition at line 130 of file AArch64.h.

◆ SCR_AW

#define SCR_AW (1 << 5)

Definition at line 46 of file AArch64.h.

◆ SCR_EA

#define SCR_EA (1 << 3)

Definition at line 44 of file AArch64.h.

◆ SCR_FIQ

#define SCR_FIQ (1 << 2)

Definition at line 43 of file AArch64.h.

◆ SCR_FW

#define SCR_FW (1 << 4)

Definition at line 45 of file AArch64.h.

◆ SCR_IRQ

#define SCR_IRQ (1 << 1)

Definition at line 42 of file AArch64.h.

◆ SCR_NS

#define SCR_NS (1 << 0)

Definition at line 41 of file AArch64.h.

◆ SPSR_A

#define SPSR_A BIT8

Definition at line 83 of file AArch64.h.

◆ SPSR_AARCH32

#define SPSR_AARCH32 BIT4

Definition at line 87 of file AArch64.h.

◆ SPSR_AARCH32_MODE_ABORT

#define SPSR_AARCH32_MODE_ABORT 0x7

Definition at line 93 of file AArch64.h.

◆ SPSR_AARCH32_MODE_FIQ

#define SPSR_AARCH32_MODE_FIQ 0x1

Definition at line 90 of file AArch64.h.

◆ SPSR_AARCH32_MODE_IRQ

#define SPSR_AARCH32_MODE_IRQ 0x2

Definition at line 91 of file AArch64.h.

◆ SPSR_AARCH32_MODE_SVC

#define SPSR_AARCH32_MODE_SVC 0x3

Definition at line 92 of file AArch64.h.

◆ SPSR_AARCH32_MODE_SYS

#define SPSR_AARCH32_MODE_SYS 0xF

Definition at line 95 of file AArch64.h.

◆ SPSR_AARCH32_MODE_UNDEF

#define SPSR_AARCH32_MODE_UNDEF 0xB

Definition at line 94 of file AArch64.h.

◆ SPSR_AARCH32_MODE_USER

#define SPSR_AARCH32_MODE_USER 0x0

Definition at line 89 of file AArch64.h.

◆ SPSR_F

#define SPSR_F BIT6

Definition at line 85 of file AArch64.h.

◆ SPSR_I

#define SPSR_I BIT7

Definition at line 84 of file AArch64.h.

◆ VECTOR_BASE

#define VECTOR_BASE ( tbl )

Value:

  .section .text.##tbl##,"ax";    \
  .align 11;                      \
  .org 0x0;                       \
  GCC_ASM_EXPORT(tbl);            \
  ASM_PFX(tbl):                   \

Definition at line 132 of file AArch64.h.

◆ VECTOR_END

#define VECTOR_END ( tbl )