TianoCore EDK2 master
Loading...
Searching...
No Matches
Callback.c
Go to the documentation of this file.
1
12#include "Snp.h"
13
28VOID
29EFIAPI
31 IN UINT64 UniqueId,
32 IN UINT32 Enable
33 )
34{
35 SNP_DRIVER *Snp;
36
37 Snp = (SNP_DRIVER *)(UINTN)UniqueId;
38 //
39 // tcpip was calling snp at tpl_notify and when we acquire a lock that was
40 // created at a lower level (TPL_CALLBACK) it gives an assert!
41 //
42 if (Enable != 0) {
43 EfiAcquireLock (&Snp->Lock);
44 } else {
45 EfiReleaseLock (&Snp->Lock);
46 }
47}
48
60VOID
61EFIAPI
63 IN UINT64 UniqueId,
64 IN UINT64 MicroSeconds
65 )
66{
67 if (MicroSeconds != 0) {
68 gBS->Stall ((UINTN)MicroSeconds);
69 }
70}
71
87VOID
88EFIAPI
90 IN UINT64 UniqueId,
91 IN UINT8 ReadOrWrite,
92 IN UINT8 NumBytes,
93 IN UINT64 MemOrPortAddr,
94 IN OUT UINT64 BufferPtr
95 )
96{
97 SNP_DRIVER *Snp;
99
100 Snp = (SNP_DRIVER *)(UINTN)UniqueId;
101
102 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)0;
103 switch (NumBytes) {
104 case 2:
105 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)1;
106 break;
107
108 case 4:
109 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)2;
110 break;
111
112 case 8:
113 Width = (EFI_PCI_IO_PROTOCOL_WIDTH)3;
114 break;
115 }
116
117 switch (ReadOrWrite) {
118 case PXE_IO_READ:
119 ASSERT (Snp->IoBarIndex < PCI_MAX_BAR);
120 if (Snp->IoBarIndex < PCI_MAX_BAR) {
121 Snp->PciIo->Io.Read (
122 Snp->PciIo,
123 Width,
124 Snp->IoBarIndex, // BAR 1 (for 32bit regs), IO base address
125 MemOrPortAddr,
126 1, // count
127 (VOID *)(UINTN)BufferPtr
128 );
129 }
130
131 break;
132
133 case PXE_IO_WRITE:
134 ASSERT (Snp->IoBarIndex < PCI_MAX_BAR);
135 if (Snp->IoBarIndex < PCI_MAX_BAR) {
136 Snp->PciIo->Io.Write (
137 Snp->PciIo,
138 Width,
139 Snp->IoBarIndex, // BAR 1 (for 32bit regs), IO base address
140 MemOrPortAddr,
141 1, // count
142 (VOID *)(UINTN)BufferPtr
143 );
144 }
145
146 break;
147
148 case PXE_MEM_READ:
149 ASSERT (Snp->MemoryBarIndex < PCI_MAX_BAR);
150 if (Snp->MemoryBarIndex < PCI_MAX_BAR) {
151 Snp->PciIo->Mem.Read (
152 Snp->PciIo,
153 Width,
154 Snp->MemoryBarIndex, // BAR 0, Memory base address
155 MemOrPortAddr,
156 1, // count
157 (VOID *)(UINTN)BufferPtr
158 );
159 }
160
161 break;
162
163 case PXE_MEM_WRITE:
164 ASSERT (Snp->MemoryBarIndex < PCI_MAX_BAR);
165 if (Snp->MemoryBarIndex < PCI_MAX_BAR) {
166 Snp->PciIo->Mem.Write (
167 Snp->PciIo,
168 Width,
169 Snp->MemoryBarIndex, // BAR 0, Memory base address
170 MemOrPortAddr,
171 1, // count
172 (VOID *)(UINTN)BufferPtr
173 );
174 }
175
176 break;
177 }
178
179 return;
180}
181
197VOID
198EFIAPI
200 IN UINT64 UniqueId,
201 IN UINT64 CpuAddr,
202 IN UINT32 NumBytes,
203 IN UINT32 Direction,
204 IN OUT UINT64 DeviceAddrPtr
205 )
206{
207 EFI_PHYSICAL_ADDRESS *DevAddrPtr;
208 EFI_PCI_IO_PROTOCOL_OPERATION DirectionFlag;
209 UINTN BuffSize;
210 SNP_DRIVER *Snp;
211 UINTN Index;
212 EFI_STATUS Status;
213
214 BuffSize = (UINTN)NumBytes;
215 Snp = (SNP_DRIVER *)(UINTN)UniqueId;
216 DevAddrPtr = (EFI_PHYSICAL_ADDRESS *)(UINTN)DeviceAddrPtr;
217
218 if (CpuAddr == 0) {
219 *DevAddrPtr = 0;
220 return;
221 }
222
223 switch (Direction) {
224 case TO_AND_FROM_DEVICE:
226 break;
227
228 case FROM_DEVICE:
229 DirectionFlag = EfiPciIoOperationBusMasterWrite;
230 break;
231
232 case TO_DEVICE:
233 DirectionFlag = EfiPciIoOperationBusMasterRead;
234 break;
235
236 default:
237 *DevAddrPtr = 0;
238 //
239 // any non zero indicates error!
240 //
241 return;
242 }
243
244 //
245 // find an unused map_list entry
246 //
247 for (Index = 0; Index < MAX_MAP_LENGTH; Index++) {
248 if (Snp->MapList[Index].VirtualAddress == 0) {
249 break;
250 }
251 }
252
253 if (Index >= MAX_MAP_LENGTH) {
254 DEBUG ((DEBUG_INFO, "SNP maplist is FULL\n"));
255 *DevAddrPtr = 0;
256 return;
257 }
258
259 Snp->MapList[Index].VirtualAddress = (EFI_PHYSICAL_ADDRESS)CpuAddr;
260
261 Status = Snp->PciIo->Map (
262 Snp->PciIo,
263 DirectionFlag,
264 (VOID *)(UINTN)CpuAddr,
265 &BuffSize,
266 DevAddrPtr,
267 &(Snp->MapList[Index].MapCookie)
268 );
269 if (Status != EFI_SUCCESS) {
270 *DevAddrPtr = 0;
271 Snp->MapList[Index].VirtualAddress = 0;
272 }
273
274 return;
275}
276
292VOID
293EFIAPI
295 IN UINT64 UniqueId,
296 IN UINT64 CpuAddr,
297 IN UINT32 NumBytes,
298 IN UINT32 Direction,
299 IN UINT64 DeviceAddr
300 )
301{
302 SNP_DRIVER *Snp;
303 UINT16 Index;
304
305 Snp = (SNP_DRIVER *)(UINTN)UniqueId;
306
307 for (Index = 0; Index < MAX_MAP_LENGTH; Index++) {
308 if (Snp->MapList[Index].VirtualAddress == CpuAddr) {
309 break;
310 }
311 }
312
313 if (Index >= MAX_MAP_LENGTH) {
314 DEBUG ((DEBUG_ERROR, "SNP could not find a mapping, failed to unmap.\n"));
315 return;
316 }
317
318 Snp->PciIo->Unmap (Snp->PciIo, Snp->MapList[Index].MapCookie);
319 Snp->MapList[Index].VirtualAddress = 0;
320 Snp->MapList[Index].MapCookie = NULL;
321 return;
322}
323
346VOID
347EFIAPI
349 IN UINT64 UniqueId,
350 IN UINT64 CpuAddr,
351 IN UINT32 NumBytes,
352 IN UINT32 Direction,
353 IN UINT64 DeviceAddr
354 )
355{
356 if ((CpuAddr == 0) || (DeviceAddr == 0) || (NumBytes == 0)) {
357 return;
358 }
359
360 switch (Direction) {
361 case FROM_DEVICE:
362 CopyMem ((UINT8 *)(UINTN)CpuAddr, (UINT8 *)(UINTN)DeviceAddr, NumBytes);
363 break;
364
365 case TO_DEVICE:
366 CopyMem ((UINT8 *)(UINTN)DeviceAddr, (UINT8 *)(UINTN)CpuAddr, NumBytes);
367 break;
368 }
369
370 return;
371}
UINT64 UINTN
VOID *EFIAPI CopyMem(OUT VOID *DestinationBuffer, IN CONST VOID *SourceBuffer, IN UINTN Length)
VOID EFIAPI SnpUndi32CallbackMap(IN UINT64 UniqueId, IN UINT64 CpuAddr, IN UINT32 NumBytes, IN UINT32 Direction, IN OUT UINT64 DeviceAddrPtr)
Definition: Callback.c:199
VOID EFIAPI SnpUndi32CallbackUnmap(IN UINT64 UniqueId, IN UINT64 CpuAddr, IN UINT32 NumBytes, IN UINT32 Direction, IN UINT64 DeviceAddr)
Definition: Callback.c:294
VOID EFIAPI SnpUndi32CallbackBlock(IN UINT64 UniqueId, IN UINT32 Enable)
Definition: Callback.c:30
VOID EFIAPI SnpUndi32CallbackMemio(IN UINT64 UniqueId, IN UINT8 ReadOrWrite, IN UINT8 NumBytes, IN UINT64 MemOrPortAddr, IN OUT UINT64 BufferPtr)
Definition: Callback.c:89
VOID EFIAPI SnpUndi32CallbackDelay(IN UINT64 UniqueId, IN UINT64 MicroSeconds)
Definition: Callback.c:62
VOID EFIAPI SnpUndi32CallbackSync(IN UINT64 UniqueId, IN UINT64 CpuAddr, IN UINT32 NumBytes, IN UINT32 Direction, IN UINT64 DeviceAddr)
Definition: Callback.c:348
#define NULL
Definition: Base.h:319
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
#define DEBUG(Expression)
Definition: DebugLib.h:434
EFI_PCI_IO_PROTOCOL_WIDTH
Definition: PciIo.h:28
EFI_PCI_IO_PROTOCOL_OPERATION
Definition: PciIo.h:77
@ EfiPciIoOperationBusMasterWrite
Definition: PciIo.h:85
@ EfiPciIoOperationBusMasterRead
Definition: PciIo.h:81
@ EfiPciIoOperationBusMasterCommonBuffer
Definition: PciIo.h:90
UINT64 EFI_PHYSICAL_ADDRESS
Definition: UefiBaseType.h:50
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
#define EFI_SUCCESS
Definition: UefiBaseType.h:112
EFI_BOOT_SERVICES * gBS
VOID EFIAPI EfiReleaseLock(IN EFI_LOCK *Lock)
Definition: UefiLib.c:499
VOID EFIAPI EfiAcquireLock(IN EFI_LOCK *Lock)
Definition: UefiLib.c:434
EFI_PCI_IO_PROTOCOL_IO_MEM Write
Definition: PciIo.h:197
EFI_PCI_IO_PROTOCOL_IO_MEM Read
Definition: PciIo.h:193
Definition: Snp.h:55