#include <Uefi.h>
#include <Base.h>
#include <IndustryStandard/Usb.h>
#include <Library/IoLib.h>
#include <IndustryStandard/Pci.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
#include <Library/DebugCommunicationLib.h>
#include <Library/PciLib.h>

Data Structures
struct	_ENDPOINT_CONTEXT_64

struct	_TRANSFER_TRB_NORMAL

struct	_EVT_TRB_TRANSFER

struct	_LINK_TRB

struct	_TRB_TEMPLATE

struct	_EVENT_RING_SEG_TABLE_ENTRY

struct	_EVENT_RING

struct	_TRANSFER_RING

struct	_DBC_INFO_CONTEXT

struct	_XHC_DC_CONTEXT

union	_TRB

struct	_URB

struct	_USB3_DEBUG_PORT_INSTANCE

Macros
#define	USB3_DBG_GUID

#define	USB3DBG_NO_DBG_CAB 0

#define	USB3DBG_DBG_CAB 1

#define	USB3DBG_ENABLED 2

#define	USB3DBG_NOT_ENABLED 4

#define	USB3DBG_UNINITIALIZED 255

#define	USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08

#define	XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400

#define	XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525

#define	XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A

#define	XHCI_DEBUG_DEVICE_PROTOCOL 0xFF

#define	XHCI_DEBUG_DEVICE_REVISION 0x00

#define	XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL

#define	XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000

#define	PCI_CAPABILITY_ID_DEBUG_PORT 0x0A

#define	XHC_HCCPARAMS_OFFSET 0x10

#define	XHC_CAPABILITY_ID_MASK 0xFF

#define	XHC_NEXT_CAPABILITY_MASK 0xFF00

#define	XHC_HCSPARAMS1_OFFSET 0x4

#define	XHC_USBCMD_OFFSET 0x0

#define	XHC_USBSTS_OFFSET 0x4

#define	XHC_PORTSC_OFFSET 0x400

#define	XHC_USBCMD_RUN BIT0

#define	XHC_USBCMD_RESET BIT1

#define	XHC_USBSTS_HALT BIT0

#define	DATA_TRANSFER_WRITE_TIMEOUT 0

#define	DATA_TRANSFER_READ_TIMEOUT 50000

#define	DATA_TRANSFER_POLL_TIMEOUT 1000

#define	XHC_DEBUG_PORT_1_MILLISECOND 1000

#define	XHC_DEBUG_PORT_ON_OFF_DELAY 100000

#define	STRING0_DESC_LEN 4

#define	MANU_DESC_LEN 12

#define	PRODUCT_DESC_LEN 40

#define	SERIAL_DESC_LEN 4

#define	XHC_DC_DCID 0x0

#define	XHC_DC_DCDB 0x4

#define	XHC_DC_DCERSTSZ 0x8

#define	XHC_DC_DCERSTBA 0x10

#define	XHC_DC_DCERDP 0x18

#define	XHC_DC_DCCTRL 0x20

#define	XHC_DC_DCST 0x24

#define	XHC_DC_DCPORTSC 0x28

#define	XHC_DC_DCCP 0x30

#define	XHC_DC_DCDDI1 0x38

#define	XHC_DC_DCDDI2 0x3C

#define	TRB_TYPE_LINK 6

#define	ERST_NUMBER 0x01

#define	TR_RING_TRB_NUMBER 0x100

#define	EVENT_RING_TRB_NUMBER 0x200

#define	ED_BULK_OUT 2

#define	ED_BULK_IN 6

#define	XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))

#define	XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))

#define	XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))

#define	ED_NOT_VALID 0

#define	ED_ISOCH_OUT 1

#define	ED_BULK_OUT 2

#define	ED_INTERRUPT_OUT 3

#define	ED_CONTROL_BIDIR 4

#define	ED_ISOCH_IN 5

#define	ED_BULK_IN 6

#define	ED_INTERRUPT_IN 7

#define	TRB_COMPLETION_INVALID 0

#define	TRB_COMPLETION_SUCCESS 1

#define	TRB_COMPLETION_DATA_BUFFER_ERROR 2

#define	TRB_COMPLETION_BABBLE_ERROR 3

#define	TRB_COMPLETION_USB_TRANSACTION_ERROR 4

#define	TRB_COMPLETION_TRB_ERROR 5

#define	TRB_COMPLETION_STALL_ERROR 6

#define	TRB_COMPLETION_SHORT_PACKET 13

#define	TRB_TYPE_NORMAL 1

#define	TRB_TYPE_SETUP_STAGE 2

#define	TRB_TYPE_DATA_STAGE 3

#define	TRB_TYPE_STATUS_STAGE 4

#define	TRB_TYPE_ISOCH 5

#define	TRB_TYPE_LINK 6

#define	TRB_TYPE_EVENT_DATA 7

#define	TRB_TYPE_NO_OP 8

#define	TRB_TYPE_EN_SLOT 9

#define	TRB_TYPE_DIS_SLOT 10

#define	TRB_TYPE_ADDRESS_DEV 11

#define	TRB_TYPE_CON_ENDPOINT 12

#define	TRB_TYPE_EVALU_CONTXT 13

#define	TRB_TYPE_RESET_ENDPOINT 14

#define	TRB_TYPE_STOP_ENDPOINT 15

#define	TRB_TYPE_SET_TR_DEQUE 16

#define	TRB_TYPE_RESET_DEV 17

#define	TRB_TYPE_GET_PORT_BANW 21

#define	TRB_TYPE_FORCE_HEADER 22

#define	TRB_TYPE_NO_OP_COMMAND 23

#define	TRB_TYPE_TRANS_EVENT 32

#define	TRB_TYPE_COMMAND_COMPLT_EVENT 33

#define	TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34

#define	TRB_TYPE_HOST_CONTROLLER_EVENT 37

#define	TRB_TYPE_DEVICE_NOTIFI_EVENT 38

#define	TRB_TYPE_MFINDEX_WRAP_EVENT 39

#define	XHC_1_MILLISECOND (1000)

#define	XHC_POLL_DELAY (1000)

#define	XHC_GENERIC_TIMEOUT (10 * 1000)

#define	EFI_USB_SPEED_FULL 0x0000
	12 Mb/s, USB 1.1 OHCI and UHCI HC.

#define	EFI_USB_SPEED_LOW 0x0001
	1 Mb/s, USB 1.1 OHCI and UHCI HC.

#define	EFI_USB_SPEED_HIGH 0x0002
	480 Mb/s, USB 2.0 EHCI HC.

#define	EFI_USB_SPEED_SUPER 0x0003
	4.8 Gb/s, USB 3.0 XHCI HC.

#define	XHC_CTRL_TRANSFER 0x01

#define	XHC_BULK_TRANSFER 0x02

#define	XHC_INT_TRANSFER_SYNC 0x04

#define	XHC_INT_TRANSFER_ASYNC 0x08

#define	XHC_INT_ONLY_TRANSFER_ASYNC 0x10

#define	EFI_USB_NOERROR 0x00

#define	EFI_USB_ERR_NOTEXECUTE 0x01

#define	EFI_USB_ERR_STALL 0x02

#define	EFI_USB_ERR_BUFFER 0x04

#define	EFI_USB_ERR_BABBLE 0x08

#define	EFI_USB_ERR_NAK 0x10

#define	EFI_USB_ERR_CRC 0x20

#define	EFI_USB_ERR_TIMEOUT 0x40

#define	EFI_USB_ERR_BITSTUFF 0x80

#define	EFI_USB_ERR_SYSTEM 0x100

Typedefs
typedef struct _ENDPOINT_CONTEXT_64	ENDPOINT_CONTEXT_64

typedef struct _TRANSFER_TRB_NORMAL	TRANSFER_TRB_NORMAL

typedef struct _EVT_TRB_TRANSFER	EVT_TRB_TRANSFER

typedef struct _LINK_TRB	LINK_TRB

typedef struct _TRB_TEMPLATE	TRB_TEMPLATE

typedef struct _EVENT_RING_SEG_TABLE_ENTRY	EVENT_RING_SEG_TABLE_ENTRY

typedef struct _EVENT_RING	EVENT_RING

typedef struct _TRANSFER_RING	TRANSFER_RING

typedef struct _DBC_INFO_CONTEXT	DBC_INFO_CONTEXT

typedef struct _XHC_DC_CONTEXT	XHC_DC_CONTEXT

typedef union _TRB	TRB

typedef struct _URB	URB

typedef struct _USB3_DEBUG_PORT_INSTANCE	USB3_DEBUG_PORT_HANDLE

Enumerations
enum	EFI_USB_DATA_DIRECTION { EfiUsbDataIn , EfiUsbDataOut , EfiUsbNoData , EfiUsbDataIn , EfiUsbDataOut , EfiUsbNoData }

Functions
UINT32	XhcReadDebugReg (IN USB3_DEBUG_PORT_HANDLE *Handle, IN UINT32 Offset)

VOID	XhcSetDebugRegBit (IN USB3_DEBUG_PORT_HANDLE *Handle, IN UINT32 Offset, IN UINT32 Bit)

VOID	XhcWriteDebugReg (IN USB3_DEBUG_PORT_HANDLE *Handle, IN UINT32 Offset, IN UINT32 Data)

BOOLEAN	XhcIsBitSet (UINTN Register, UINT32 BitMask)

VOID	XhcSetR32Bit (UINTN Register, UINT32 BitMask)

VOID	XhcClearR32Bit (IN OUT UINTN Register, IN UINT32 BitMask)

RETURN_STATUS EFIAPI	USB3Initialize (VOID)

UINT16	GetXhciPciCommand (VOID)

VOID *	AllocateAlignBuffer (IN UINTN BufferSize)

RETURN_STATUS EFIAPI	USB3InitializeReal (VOID)

EFI_STATUS EFIAPI	XhcDataTransfer (IN USB3_DEBUG_PORT_HANDLE Handle, IN EFI_USB_DATA_DIRECTION Direction, IN OUT VOID Data, IN OUT UINTN *DataLength, IN UINTN Timeout)

RETURN_STATUS EFIAPI	InitializeUsbDebugHardware (IN USB3_DEBUG_PORT_HANDLE *Handle)

EFI_PHYSICAL_ADDRESS *	GetUsb3DebugPortInstanceAddrPtr (VOID)

USB3_DEBUG_PORT_HANDLE *	GetUsb3DebugPortInstance (VOID)

Detailed Description

Debug Port Library implementation based on usb3 debug port.

Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file DebugCommunicationLibUsb3Internal.h.

Macro Definition Documentation

◆ DATA_TRANSFER_POLL_TIMEOUT

#define DATA_TRANSFER_POLL_TIMEOUT 1000

Definition at line 80 of file DebugCommunicationLibUsb3Internal.h.

◆ DATA_TRANSFER_READ_TIMEOUT

#define DATA_TRANSFER_READ_TIMEOUT 50000

Definition at line 79 of file DebugCommunicationLibUsb3Internal.h.

◆ DATA_TRANSFER_WRITE_TIMEOUT

#define DATA_TRANSFER_WRITE_TIMEOUT 0

Definition at line 78 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_BULK_IN [1/2]

#define ED_BULK_IN 6

Definition at line 132 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_BULK_IN [2/2]

#define ED_BULK_IN 6

Definition at line 132 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_BULK_OUT [1/2]

#define ED_BULK_OUT 2

Definition at line 128 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_BULK_OUT [2/2]

#define ED_BULK_OUT 2

Definition at line 128 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_CONTROL_BIDIR

#define ED_CONTROL_BIDIR 4

Definition at line 130 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_INTERRUPT_IN

#define ED_INTERRUPT_IN 7

Definition at line 133 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_INTERRUPT_OUT

#define ED_INTERRUPT_OUT 3

Definition at line 129 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_ISOCH_IN

#define ED_ISOCH_IN 5

Definition at line 131 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_ISOCH_OUT

#define ED_ISOCH_OUT 1

Definition at line 127 of file DebugCommunicationLibUsb3Internal.h.

◆ ED_NOT_VALID

#define ED_NOT_VALID 0

Definition at line 126 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_BABBLE

#define EFI_USB_ERR_BABBLE 0x08

Definition at line 205 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_BITSTUFF

#define EFI_USB_ERR_BITSTUFF 0x80

Definition at line 209 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_BUFFER

#define EFI_USB_ERR_BUFFER 0x04

Definition at line 204 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_CRC

#define EFI_USB_ERR_CRC 0x20

Definition at line 207 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_NAK

#define EFI_USB_ERR_NAK 0x10

Definition at line 206 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_NOTEXECUTE

#define EFI_USB_ERR_NOTEXECUTE 0x01

Definition at line 202 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_STALL

#define EFI_USB_ERR_STALL 0x02

Definition at line 203 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_SYSTEM

#define EFI_USB_ERR_SYSTEM 0x100

Definition at line 210 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_ERR_TIMEOUT

#define EFI_USB_ERR_TIMEOUT 0x40

Definition at line 208 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_NOERROR

#define EFI_USB_NOERROR 0x00

Definition at line 201 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_SPEED_FULL

#define EFI_USB_SPEED_FULL 0x0000

12 Mb/s, USB 1.1 OHCI and UHCI HC.

Definition at line 184 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_SPEED_HIGH

#define EFI_USB_SPEED_HIGH 0x0002

480 Mb/s, USB 2.0 EHCI HC.

Definition at line 186 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_SPEED_LOW

#define EFI_USB_SPEED_LOW 0x0001

1 Mb/s, USB 1.1 OHCI and UHCI HC.

Definition at line 185 of file DebugCommunicationLibUsb3Internal.h.

◆ EFI_USB_SPEED_SUPER

#define EFI_USB_SPEED_SUPER 0x0003

4.8 Gb/s, USB 3.0 XHCI HC.

Definition at line 187 of file DebugCommunicationLibUsb3Internal.h.

◆ ERST_NUMBER

#define ERST_NUMBER 0x01

Definition at line 112 of file DebugCommunicationLibUsb3Internal.h.

◆ EVENT_RING_TRB_NUMBER

#define EVENT_RING_TRB_NUMBER 0x200

Definition at line 114 of file DebugCommunicationLibUsb3Internal.h.

◆ MANU_DESC_LEN

#define MANU_DESC_LEN 12

Definition at line 91 of file DebugCommunicationLibUsb3Internal.h.

◆ PCI_CAPABILITY_ID_DEBUG_PORT

#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A

Definition at line 60 of file DebugCommunicationLibUsb3Internal.h.

◆ PRODUCT_DESC_LEN

#define PRODUCT_DESC_LEN 40

Definition at line 92 of file DebugCommunicationLibUsb3Internal.h.

◆ SERIAL_DESC_LEN

#define SERIAL_DESC_LEN 4

Definition at line 93 of file DebugCommunicationLibUsb3Internal.h.

◆ STRING0_DESC_LEN

#define STRING0_DESC_LEN 4

Definition at line 90 of file DebugCommunicationLibUsb3Internal.h.

◆ TR_RING_TRB_NUMBER

#define TR_RING_TRB_NUMBER 0x100

Definition at line 113 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_BABBLE_ERROR

#define TRB_COMPLETION_BABBLE_ERROR 3

Definition at line 141 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_DATA_BUFFER_ERROR

#define TRB_COMPLETION_DATA_BUFFER_ERROR 2

Definition at line 140 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_INVALID

#define TRB_COMPLETION_INVALID 0

Definition at line 138 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_SHORT_PACKET

#define TRB_COMPLETION_SHORT_PACKET 13

Definition at line 145 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_STALL_ERROR

#define TRB_COMPLETION_STALL_ERROR 6

Definition at line 144 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_SUCCESS

#define TRB_COMPLETION_SUCCESS 1

Definition at line 139 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_TRB_ERROR

#define TRB_COMPLETION_TRB_ERROR 5

Definition at line 143 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_COMPLETION_USB_TRANSACTION_ERROR

#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4

Definition at line 142 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_ADDRESS_DEV

#define TRB_TYPE_ADDRESS_DEV 11

Definition at line 160 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_COMMAND_COMPLT_EVENT

#define TRB_TYPE_COMMAND_COMPLT_EVENT 33

Definition at line 171 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_CON_ENDPOINT

#define TRB_TYPE_CON_ENDPOINT 12

Definition at line 161 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_DATA_STAGE

#define TRB_TYPE_DATA_STAGE 3

Definition at line 152 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_DEVICE_NOTIFI_EVENT

#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38

Definition at line 174 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_DIS_SLOT

#define TRB_TYPE_DIS_SLOT 10

Definition at line 159 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_EN_SLOT

#define TRB_TYPE_EN_SLOT 9

Definition at line 158 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_EVALU_CONTXT

#define TRB_TYPE_EVALU_CONTXT 13

Definition at line 162 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_EVENT_DATA

#define TRB_TYPE_EVENT_DATA 7

Definition at line 156 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_FORCE_HEADER

#define TRB_TYPE_FORCE_HEADER 22

Definition at line 168 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_GET_PORT_BANW

#define TRB_TYPE_GET_PORT_BANW 21

Definition at line 167 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_HOST_CONTROLLER_EVENT

#define TRB_TYPE_HOST_CONTROLLER_EVENT 37

Definition at line 173 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_ISOCH

#define TRB_TYPE_ISOCH 5

Definition at line 154 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_LINK [1/2]

#define TRB_TYPE_LINK 6

Definition at line 155 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_LINK [2/2]

#define TRB_TYPE_LINK 6

Definition at line 155 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_MFINDEX_WRAP_EVENT

#define TRB_TYPE_MFINDEX_WRAP_EVENT 39

Definition at line 175 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_NO_OP

#define TRB_TYPE_NO_OP 8

Definition at line 157 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_NO_OP_COMMAND

#define TRB_TYPE_NO_OP_COMMAND 23

Definition at line 169 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_NORMAL

#define TRB_TYPE_NORMAL 1

Definition at line 150 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_PORT_STATUS_CHANGE_EVENT

#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34

Definition at line 172 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_RESET_DEV

#define TRB_TYPE_RESET_DEV 17

Definition at line 166 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_RESET_ENDPOINT

#define TRB_TYPE_RESET_ENDPOINT 14

Definition at line 163 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_SET_TR_DEQUE

#define TRB_TYPE_SET_TR_DEQUE 16

Definition at line 165 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_SETUP_STAGE

#define TRB_TYPE_SETUP_STAGE 2

Definition at line 151 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_STATUS_STAGE

#define TRB_TYPE_STATUS_STAGE 4

Definition at line 153 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_STOP_ENDPOINT

#define TRB_TYPE_STOP_ENDPOINT 15

Definition at line 164 of file DebugCommunicationLibUsb3Internal.h.

◆ TRB_TYPE_TRANS_EVENT

#define TRB_TYPE_TRANS_EVENT 32

Definition at line 170 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3_DBG_GUID

#define USB3_DBG_GUID

Value:

    { \
      0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \
    }

Definition at line 31 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE

#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08

Definition at line 45 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3DBG_DBG_CAB

#define USB3DBG_DBG_CAB 1

Definition at line 40 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3DBG_ENABLED

#define USB3DBG_ENABLED 2

Definition at line 41 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3DBG_NO_DBG_CAB

#define USB3DBG_NO_DBG_CAB 0

Definition at line 39 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3DBG_NOT_ENABLED

#define USB3DBG_NOT_ENABLED 4

Definition at line 42 of file DebugCommunicationLibUsb3Internal.h.

◆ USB3DBG_UNINITIALIZED

#define USB3DBG_UNINITIALIZED 255

Definition at line 43 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_1_MILLISECOND

#define XHC_1_MILLISECOND (1000)

Definition at line 180 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_BIT_IS_SET

#define XHC_BIT_IS_SET	(	Data,
		Bit
	)	((BOOLEAN)(((Data) & (Bit)) == (Bit)))

Definition at line 121 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_BULK_TRANSFER

#define XHC_BULK_TRANSFER 0x02

Definition at line 193 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_CAPABILITY_ID_MASK

#define XHC_CAPABILITY_ID_MASK 0xFF

Definition at line 62 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_CTRL_TRANSFER

#define XHC_CTRL_TRANSFER 0x01

Definition at line 192 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCCP

#define XHC_DC_DCCP 0x30

Definition at line 106 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCCTRL

#define XHC_DC_DCCTRL 0x20

Definition at line 103 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCDB

#define XHC_DC_DCDB 0x4

Definition at line 99 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCDDI1

#define XHC_DC_DCDDI1 0x38

Definition at line 107 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCDDI2

#define XHC_DC_DCDDI2 0x3C

Definition at line 108 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCERDP

#define XHC_DC_DCERDP 0x18

Definition at line 102 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCERSTBA

#define XHC_DC_DCERSTBA 0x10

Definition at line 101 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCERSTSZ

#define XHC_DC_DCERSTSZ 0x8

Definition at line 100 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCID

#define XHC_DC_DCID 0x0

Definition at line 98 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCPORTSC

#define XHC_DC_DCPORTSC 0x28

Definition at line 105 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DC_DCST

#define XHC_DC_DCST 0x24

Definition at line 104 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DEBUG_PORT_1_MILLISECOND

#define XHC_DEBUG_PORT_1_MILLISECOND 1000

Definition at line 81 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_DEBUG_PORT_ON_OFF_DELAY

#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000

Definition at line 85 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_GENERIC_TIMEOUT

#define XHC_GENERIC_TIMEOUT (10 * 1000)

Definition at line 182 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_HCCPARAMS_OFFSET

#define XHC_HCCPARAMS_OFFSET 0x10

Definition at line 61 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_HCSPARAMS1_OFFSET

#define XHC_HCSPARAMS1_OFFSET 0x4

Definition at line 65 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_HIGH_32BIT

#define XHC_HIGH_32BIT ( Addr64 ) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))

Definition at line 120 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_INT_ONLY_TRANSFER_ASYNC

#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10

Definition at line 196 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_INT_TRANSFER_ASYNC

#define XHC_INT_TRANSFER_ASYNC 0x08

Definition at line 195 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_INT_TRANSFER_SYNC

#define XHC_INT_TRANSFER_SYNC 0x04

Definition at line 194 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_LOW_32BIT

#define XHC_LOW_32BIT ( Addr64 ) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))

Definition at line 119 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_NEXT_CAPABILITY_MASK

#define XHC_NEXT_CAPABILITY_MASK 0xFF00

Definition at line 63 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_POLL_DELAY

#define XHC_POLL_DELAY (1000)

Definition at line 181 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_PORTSC_OFFSET

#define XHC_PORTSC_OFFSET 0x400

Definition at line 68 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_USBCMD_OFFSET

#define XHC_USBCMD_OFFSET 0x0

Definition at line 66 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_USBCMD_RESET

#define XHC_USBCMD_RESET BIT1

Definition at line 71 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_USBCMD_RUN

#define XHC_USBCMD_RUN BIT0

Definition at line 70 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_USBSTS_HALT

#define XHC_USBSTS_HALT BIT0

Definition at line 73 of file DebugCommunicationLibUsb3Internal.h.

◆ XHC_USBSTS_OFFSET

#define XHC_USBSTS_OFFSET 0x4

Definition at line 67 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_BASE_ADDRESS_32_BIT_MASK

#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000

Definition at line 58 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_BASE_ADDRESS_64_BIT_MASK

#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL

Definition at line 57 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE

#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400

Definition at line 50 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_DEBUG_DEVICE_PRODUCT_ID

#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A

Definition at line 53 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_DEBUG_DEVICE_PROTOCOL

#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF

Definition at line 54 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_DEBUG_DEVICE_REVISION

#define XHCI_DEBUG_DEVICE_REVISION 0x00

Definition at line 55 of file DebugCommunicationLibUsb3Internal.h.

◆ XHCI_DEBUG_DEVICE_VENDOR_ID

#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525

Definition at line 52 of file DebugCommunicationLibUsb3Internal.h.

Enumeration Type Documentation

◆ EFI_USB_DATA_DIRECTION

enum EFI_USB_DATA_DIRECTION

USB data transfer direction

Definition at line 416 of file DebugCommunicationLibUsb3Internal.h.

Function Documentation

◆ AllocateAlignBuffer()

VOID * AllocateAlignBuffer ( IN UINTN BufferSize )

Allocate aligned memory for XHC's usage.

Parameters

BufferSize The size, in bytes, of the Buffer.

Returns: A pointer to the allocated buffer or NULL if allocation fails.

Definition at line 397 of file DebugCommunicationLibUsb3Dxe.c.

◆ GetUsb3DebugPortInstance()

USB3_DEBUG_PORT_HANDLE * GetUsb3DebugPortInstance ( VOID )

Return USB3 debug instance address.

Definition at line 842 of file DebugCommunicationLibUsb3Common.c.

◆ GetUsb3DebugPortInstanceAddrPtr()

EFI_PHYSICAL_ADDRESS * GetUsb3DebugPortInstanceAddrPtr ( VOID )

Return USB3 debug instance address pointer.

Definition at line 328 of file DebugCommunicationLibUsb3Dxe.c.

◆ GetXhciPciCommand()

UINT16 GetXhciPciCommand ( VOID )

Return command register value in XHCI controller.

◆ InitializeUsbDebugHardware()

RETURN_STATUS EFIAPI InitializeUsbDebugHardware ( IN USB3_DEBUG_PORT_HANDLE * Handle )

Initialize usb debug port hardware.

Parameters

Handle Debug port handle.

Return values

TRUE	The usb debug port hardware configuration is changed.
FALSE	The usb debug port hardware configuration is not changed.

Definition at line 664 of file DebugCommunicationLibUsb3Common.c.

◆ USB3Initialize()

RETURN_STATUS EFIAPI USB3Initialize ( VOID )

Initialize USB3 debug port.

This method invokes various internal functions to facilitate detection and initialization of USB3 debug port.

Return values

RETURN_SUCCESS The serial device was initialized.

◆ USB3InitializeReal()

RETURN_STATUS EFIAPI USB3InitializeReal ( VOID )

The real function to initialize USB3 debug port.

This method invokes various internal functions to facilitate detection and initialization of USB3 debug port.

Return values

RETURN_SUCCESS The serial device was initialized.

◆ XhcClearR32Bit()

VOID XhcClearR32Bit	(	IN OUT UINTN	Register,
		IN UINT32	BitMask
	)

Clears bits as per the enabled bit positions in the mask.

Parameters

[in,out]	Register	UINTN register
[in]	BitMask	32-bit mask

Definition at line 61 of file DebugCommunicationLibUsb3Common.c.

◆ XhcDataTransfer()

EFI_STATUS EFIAPI XhcDataTransfer	(	IN USB3_DEBUG_PORT_HANDLE *	Handle,
		IN EFI_USB_DATA_DIRECTION	Direction,
		IN OUT VOID *	Data,
		IN OUT UINTN *	DataLength,
		IN UINTN	Timeout
	)

Submits bulk transfer to a bulk endpoint of a USB device.

Parameters

Handle	The instance of debug device.
Direction	The direction of data transfer.
Data	Array of pointers to the buffers of data to transmit from or receive into.
DataLength	The length of the data buffer.
Timeout	Indicates the maximum time, in millisecond, which the transfer is allowed to complete.

Return values

EFI_SUCCESS	The transfer was completed successfully.
EFI_OUT_OF_RESOURCES	The transfer failed due to lack of resource.
EFI_INVALID_PARAMETER	Some parameters are invalid.
EFI_TIMEOUT	The transfer failed due to timeout.
EFI_DEVICE_ERROR	The transfer failed due to host controller error.

Submits bulk transfer to a bulk endpoint of a USB device.

Parameters

Handle	Debug port handle.
Direction	The direction of data transfer.
Data	Array of pointers to the buffers of data to transmit from or receive into.
DataLength	The length of the data buffer.
Timeout	Indicates the maximum time, in microsecond, which the transfer is allowed to complete.

Return values

EFI_SUCCESS	The transfer was completed successfully.
EFI_OUT_OF_RESOURCES	The transfer failed due to lack of resource.
EFI_INVALID_PARAMETER	Some parameters are invalid.
EFI_TIMEOUT	The transfer failed due to timeout.
EFI_DEVICE_ERROR	The transfer failed due to host controller error.

Definition at line 534 of file DebugCommunicationLibUsb3Transfer.c.

◆ XhcIsBitSet()

BOOLEAN XhcIsBitSet	(	UINTN	Register,
		UINT32	BitMask
	)

Verifies if the bit positions specified by a mask are set in a register.

Parameters

[in,out]	Register	UINTN register
[in]	BitMask	32-bit mask

Returns

BOOLEAN - TRUE if all bits specified by the mask are enabled.

FALSE even if one of the bits specified by the mask is not enabled.

◆ XhcReadDebugReg()

UINT32 XhcReadDebugReg	(	IN USB3_DEBUG_PORT_HANDLE *	Handle,
		IN UINT32	Offset
	)

Read XHCI debug register.

Parameters

Handle	Debug port handle.
Offset	The offset of the debug register.

Returns: The register content read

Read XHCI debug register.

Parameters

Handle	Debug port handle.
Offset	The offset of the runtime register.

Returns: The register content read

Definition at line 106 of file DebugCommunicationLibUsb3Common.c.

◆ XhcSetDebugRegBit()

VOID XhcSetDebugRegBit	(	IN USB3_DEBUG_PORT_HANDLE *	Handle,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Set one bit of the debug register while keeping other bits.

Parameters

Handle	Debug port handle.
Offset	The offset of the debug register.
Bit	The bit mask of the register to set.

Definition at line 129 of file DebugCommunicationLibUsb3Common.c.

◆ XhcSetR32Bit()

VOID XhcSetR32Bit	(	UINTN	Register,
		UINT32	BitMask
	)

Sets bits as per the enabled bit positions in the mask.

Parameters

[in,out]	Register	UINTN register
[in]	BitMask	32-bit mask

◆ XhcWriteDebugReg()

VOID XhcWriteDebugReg	(	IN USB3_DEBUG_PORT_HANDLE *	Handle,
		IN UINT32	Offset,
		IN UINT32	Data
	)

Write the data to the debug register.

Parameters

Handle	Debug port handle.
Offset	The offset of the debug register.
Data	The data to write.

Write the data to the XHCI debug register.

Parameters

Handle	Debug port handle.
Offset	The offset of the debug register.
Data	The data to write.

Definition at line 82 of file DebugCommunicationLibUsb3Common.c.

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ DATA_TRANSFER_POLL_TIMEOUT

◆ DATA_TRANSFER_READ_TIMEOUT

◆ DATA_TRANSFER_WRITE_TIMEOUT

◆ ED_BULK_IN [1/2]

◆ ED_BULK_IN [2/2]

◆ ED_BULK_OUT [1/2]

◆ ED_BULK_OUT [2/2]

◆ ED_CONTROL_BIDIR

◆ ED_INTERRUPT_IN

◆ ED_INTERRUPT_OUT

◆ ED_ISOCH_IN

◆ ED_ISOCH_OUT

◆ ED_NOT_VALID

◆ EFI_USB_ERR_BABBLE

◆ EFI_USB_ERR_BITSTUFF

◆ EFI_USB_ERR_BUFFER

◆ EFI_USB_ERR_CRC

◆ EFI_USB_ERR_NAK

◆ EFI_USB_ERR_NOTEXECUTE

◆ EFI_USB_ERR_STALL

◆ EFI_USB_ERR_SYSTEM

◆ EFI_USB_ERR_TIMEOUT

◆ EFI_USB_NOERROR

◆ EFI_USB_SPEED_FULL

◆ EFI_USB_SPEED_HIGH

◆ EFI_USB_SPEED_LOW

◆ EFI_USB_SPEED_SUPER

◆ ERST_NUMBER

◆ EVENT_RING_TRB_NUMBER

◆ MANU_DESC_LEN

◆ PCI_CAPABILITY_ID_DEBUG_PORT

◆ PRODUCT_DESC_LEN

◆ SERIAL_DESC_LEN

◆ STRING0_DESC_LEN

◆ TR_RING_TRB_NUMBER

◆ TRB_COMPLETION_BABBLE_ERROR

◆ TRB_COMPLETION_DATA_BUFFER_ERROR

◆ TRB_COMPLETION_INVALID

◆ TRB_COMPLETION_SHORT_PACKET

◆ TRB_COMPLETION_STALL_ERROR

◆ TRB_COMPLETION_SUCCESS

◆ TRB_COMPLETION_TRB_ERROR

◆ TRB_COMPLETION_USB_TRANSACTION_ERROR

◆ TRB_TYPE_ADDRESS_DEV

◆ TRB_TYPE_COMMAND_COMPLT_EVENT

◆ TRB_TYPE_CON_ENDPOINT

◆ TRB_TYPE_DATA_STAGE

◆ TRB_TYPE_DEVICE_NOTIFI_EVENT

◆ TRB_TYPE_DIS_SLOT

◆ TRB_TYPE_EN_SLOT

◆ TRB_TYPE_EVALU_CONTXT

◆ TRB_TYPE_EVENT_DATA

◆ TRB_TYPE_FORCE_HEADER

◆ TRB_TYPE_GET_PORT_BANW

◆ TRB_TYPE_HOST_CONTROLLER_EVENT

◆ TRB_TYPE_ISOCH

◆ TRB_TYPE_LINK [1/2]

◆ TRB_TYPE_LINK [2/2]

◆ TRB_TYPE_MFINDEX_WRAP_EVENT

◆ TRB_TYPE_NO_OP

◆ TRB_TYPE_NO_OP_COMMAND

◆ TRB_TYPE_NORMAL

◆ TRB_TYPE_PORT_STATUS_CHANGE_EVENT

◆ TRB_TYPE_RESET_DEV

◆ TRB_TYPE_RESET_ENDPOINT

◆ TRB_TYPE_SET_TR_DEQUE

◆ TRB_TYPE_SETUP_STAGE

◆ TRB_TYPE_STATUS_STAGE

◆ TRB_TYPE_STOP_ENDPOINT

◆ TRB_TYPE_TRANS_EVENT

◆ USB3_DBG_GUID

◆ USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE

◆ USB3DBG_DBG_CAB