Data Structures
struct	USB_PORT_STATE_MAP

struct	USB_CLASSC

Macros
#define	EHC_CAPLENGTH_OFFSET 0

#define	EHC_HCSPARAMS_OFFSET 0x04

#define	EHC_HCCPARAMS_OFFSET 0x08

#define	HCSP_NPORTS 0x0F

#define	HCSP_PPC 0x10

#define	HCCP_64BIT 0x01

#define	EHC_USBCMD_OFFSET 0x0

#define	EHC_USBSTS_OFFSET 0x04

#define	EHC_USBINTR_OFFSET 0x08

#define	EHC_FRINDEX_OFFSET 0x0C

#define	EHC_CTRLDSSEG_OFFSET 0x10

#define	EHC_FRAME_BASE_OFFSET 0x14

#define	EHC_ASYNC_HEAD_OFFSET 0x18

#define	EHC_CONFIG_FLAG_OFFSET 0x40

#define	EHC_PORT_STAT_OFFSET 0x44

#define	EHC_FRAME_LEN 1024

#define	CONFIGFLAG_ROUTE_EHC 0x01

#define	USBCMD_RUN 0x01

#define	USBCMD_RESET 0x02

#define	USBCMD_ENABLE_PERIOD 0x10

#define	USBCMD_ENABLE_ASYNC 0x20

#define	USBCMD_IAAD 0x40

#define	USBSTS_IAA 0x20

#define	USBSTS_PERIOD_ENABLED 0x4000

#define	USBSTS_ASYNC_ENABLED 0x8000

#define	USBSTS_HALT 0x1000

#define	USBSTS_SYS_ERROR 0x10

#define	USBSTS_INTACK_MASK 0x003F

#define	PORTSC_CONN 0x01

#define	PORTSC_CONN_CHANGE 0x02

#define	PORTSC_ENABLED 0x04

#define	PORTSC_ENABLE_CHANGE 0x08

#define	PORTSC_OVERCUR 0x10

#define	PORTSC_OVERCUR_CHANGE 0x20

#define	PORSTSC_RESUME 0x40

#define	PORTSC_SUSPEND 0x80

#define	PORTSC_RESET 0x100

#define	PORTSC_LINESTATE_K 0x400

#define	PORTSC_LINESTATE_J 0x800

#define	PORTSC_POWER 0x1000

#define	PORTSC_OWNER 0x2000

#define	PORTSC_CHANGE_MASK 0x2A

#define	EHC_BAR_INDEX 0

#define	EHC_DEBUG_PORT_CAP_ID 0x0A

#define	EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)

#define	EHC_ADDR(High, QhHw32) ((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))

#define	EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)

Functions
UINT32	EhcReadCapRegister (IN USB2_HC_DEV *Ehc, IN UINT32 Offset)

BOOLEAN	EhcIsDebugPortInUse (IN CONST USB2_HC_DEV Ehc, IN CONST UINT8 PortNumber OPTIONAL)

UINT32	EhcReadOpReg (IN USB2_HC_DEV *Ehc, IN UINT32 Offset)

VOID	EhcWriteOpReg (IN USB2_HC_DEV *Ehc, IN UINT32 Offset, IN UINT32 Data)

VOID	EhcSetOpRegBit (IN USB2_HC_DEV *Ehc, IN UINT32 Offset, IN UINT32 Bit)

VOID	EhcClearOpRegBit (IN USB2_HC_DEV *Ehc, IN UINT32 Offset, IN UINT32 Bit)

VOID	EhcClearLegacySupport (IN USB2_HC_DEV *Ehc)

EFI_STATUS	EhcSetAndWaitDoorBell (IN USB2_HC_DEV *Ehc, IN UINT32 Timeout)

VOID	EhcAckAllInterrupt (IN USB2_HC_DEV *Ehc)

BOOLEAN	EhcIsHalt (IN USB2_HC_DEV *Ehc)

BOOLEAN	EhcIsSysError (IN USB2_HC_DEV *Ehc)

EFI_STATUS	EhcResetHC (IN USB2_HC_DEV *Ehc, IN UINT32 Timeout)

EFI_STATUS	EhcHaltHC (IN USB2_HC_DEV *Ehc, IN UINT32 Timeout)

EFI_STATUS	EhcRunHC (IN USB2_HC_DEV *Ehc, IN UINT32 Timeout)

EFI_STATUS	EhcInitHC (IN USB2_HC_DEV *Ehc)

Detailed Description

This file contains the definination for host controller register operation routines.

Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file EhciReg.h.

Macro Definition Documentation

◆ CONFIGFLAG_ROUTE_EHC

#define CONFIGFLAG_ROUTE_EHC 0x01

Definition at line 49 of file EhciReg.h.

◆ EHC_ADDR

#define EHC_ADDR	(	High,
		QhHw32
	)	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))

Definition at line 92 of file EhciReg.h.

◆ EHC_ASYNC_HEAD_OFFSET

#define EHC_ASYNC_HEAD_OFFSET 0x18

Definition at line 40 of file EhciReg.h.

◆ EHC_BAR_INDEX

#define EHC_BAR_INDEX 0

Definition at line 83 of file EhciReg.h.

◆ EHC_CAPLENGTH_OFFSET

#define EHC_CAPLENGTH_OFFSET 0

Definition at line 20 of file EhciReg.h.

◆ EHC_CONFIG_FLAG_OFFSET

#define EHC_CONFIG_FLAG_OFFSET 0x40

Definition at line 41 of file EhciReg.h.

◆ EHC_CTRLDSSEG_OFFSET

#define EHC_CTRLDSSEG_OFFSET 0x10

Definition at line 38 of file EhciReg.h.

◆ EHC_DEBUG_PORT_CAP_ID

#define EHC_DEBUG_PORT_CAP_ID 0x0A

Definition at line 88 of file EhciReg.h.

◆ EHC_FRAME_BASE_OFFSET

#define EHC_FRAME_BASE_OFFSET 0x14

Definition at line 39 of file EhciReg.h.

◆ EHC_FRAME_LEN

#define EHC_FRAME_LEN 1024

Definition at line 44 of file EhciReg.h.

◆ EHC_FRINDEX_OFFSET

#define EHC_FRINDEX_OFFSET 0x0C

Definition at line 37 of file EhciReg.h.

◆ EHC_HCCPARAMS_OFFSET

#define EHC_HCCPARAMS_OFFSET 0x08

Definition at line 22 of file EhciReg.h.

◆ EHC_HCSPARAMS_OFFSET

#define EHC_HCSPARAMS_OFFSET 0x04

Definition at line 21 of file EhciReg.h.

◆ EHC_LINK_TERMINATED

#define EHC_LINK_TERMINATED ( Link ) (((Link) & 0x01) != 0)

Definition at line 90 of file EhciReg.h.

◆ EHC_PORT_STAT_OFFSET

#define EHC_PORT_STAT_OFFSET 0x44

Definition at line 42 of file EhciReg.h.

◆ EHC_USBCMD_OFFSET

#define EHC_USBCMD_OFFSET 0x0

Definition at line 34 of file EhciReg.h.

◆ EHC_USBINTR_OFFSET

#define EHC_USBINTR_OFFSET 0x08

Definition at line 36 of file EhciReg.h.

◆ EHC_USBSTS_OFFSET

#define EHC_USBSTS_OFFSET 0x04

Definition at line 35 of file EhciReg.h.

◆ EHCI_IS_DATAIN

#define EHCI_IS_DATAIN ( EndpointAddr ) EHC_BIT_IS_SET((EndpointAddr), 0x80)

Definition at line 95 of file EhciReg.h.

◆ HCCP_64BIT

#define HCCP_64BIT 0x01

Definition at line 29 of file EhciReg.h.

◆ HCSP_NPORTS

#define HCSP_NPORTS 0x0F

Definition at line 27 of file EhciReg.h.

◆ HCSP_PPC

#define HCSP_PPC 0x10

Definition at line 28 of file EhciReg.h.

◆ PORSTSC_RESUME

#define PORSTSC_RESUME 0x40

Definition at line 71 of file EhciReg.h.

◆ PORTSC_CHANGE_MASK

#define PORTSC_CHANGE_MASK 0x2A

Definition at line 78 of file EhciReg.h.

◆ PORTSC_CONN

#define PORTSC_CONN 0x01

Definition at line 65 of file EhciReg.h.

◆ PORTSC_CONN_CHANGE

#define PORTSC_CONN_CHANGE 0x02

Definition at line 66 of file EhciReg.h.

◆ PORTSC_ENABLE_CHANGE

#define PORTSC_ENABLE_CHANGE 0x08

Definition at line 68 of file EhciReg.h.

◆ PORTSC_ENABLED

#define PORTSC_ENABLED 0x04

Definition at line 67 of file EhciReg.h.

◆ PORTSC_LINESTATE_J

#define PORTSC_LINESTATE_J 0x800

Definition at line 75 of file EhciReg.h.

◆ PORTSC_LINESTATE_K

#define PORTSC_LINESTATE_K 0x400

Definition at line 74 of file EhciReg.h.

◆ PORTSC_OVERCUR

#define PORTSC_OVERCUR 0x10

Definition at line 69 of file EhciReg.h.

◆ PORTSC_OVERCUR_CHANGE

#define PORTSC_OVERCUR_CHANGE 0x20

Definition at line 70 of file EhciReg.h.

◆ PORTSC_OWNER

#define PORTSC_OWNER 0x2000

Definition at line 77 of file EhciReg.h.

◆ PORTSC_POWER

#define PORTSC_POWER 0x1000

Definition at line 76 of file EhciReg.h.

◆ PORTSC_RESET

#define PORTSC_RESET 0x100

Definition at line 73 of file EhciReg.h.

◆ PORTSC_SUSPEND

#define PORTSC_SUSPEND 0x80

Definition at line 72 of file EhciReg.h.

◆ USBCMD_ENABLE_ASYNC

#define USBCMD_ENABLE_ASYNC 0x20

Definition at line 54 of file EhciReg.h.

◆ USBCMD_ENABLE_PERIOD

#define USBCMD_ENABLE_PERIOD 0x10

Definition at line 53 of file EhciReg.h.

◆ USBCMD_IAAD

#define USBCMD_IAAD 0x40

Definition at line 55 of file EhciReg.h.

◆ USBCMD_RESET

#define USBCMD_RESET 0x02

Definition at line 52 of file EhciReg.h.

◆ USBCMD_RUN

#define USBCMD_RUN 0x01

Definition at line 51 of file EhciReg.h.

◆ USBSTS_ASYNC_ENABLED

#define USBSTS_ASYNC_ENABLED 0x8000

Definition at line 59 of file EhciReg.h.

◆ USBSTS_HALT

#define USBSTS_HALT 0x1000

Definition at line 60 of file EhciReg.h.

◆ USBSTS_IAA

#define USBSTS_IAA 0x20

Definition at line 57 of file EhciReg.h.

◆ USBSTS_INTACK_MASK

#define USBSTS_INTACK_MASK 0x003F

Definition at line 62 of file EhciReg.h.

◆ USBSTS_PERIOD_ENABLED

#define USBSTS_PERIOD_ENABLED 0x4000

Definition at line 58 of file EhciReg.h.

◆ USBSTS_SYS_ERROR

#define USBSTS_SYS_ERROR 0x10

Definition at line 61 of file EhciReg.h.

Function Documentation

◆ EhcAckAllInterrupt()

VOID EhcAckAllInterrupt ( IN USB2_HC_DEV * Ehc )

Clear all the interrutp status bits, these bits are Write-Clean.

Parameters

Ehc	The EHCI device.

Definition at line 376 of file EhciReg.c.

◆ EhcClearLegacySupport()

VOID EhcClearLegacySupport ( IN USB2_HC_DEV * Ehc )

Add support for UEFI Over Legacy (UoL) feature, stop the legacy USB SMI support.

Parameters

Ehc	The EHCI device.

Definition at line 295 of file EhciReg.c.

◆ EhcClearOpRegBit()

VOID EhcClearOpRegBit	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Clear one bit of the operational register while keeping other bits.

Parameters

Ehc	The EHCI device.
Offset	The offset of the operational register.
Bit	The bit mask of the register to clear.

Definition at line 238 of file EhciReg.c.

◆ EhcHaltHC()

EFI_STATUS EhcHaltHC	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Halt the host controller.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Returns: EFI_SUCCESS The EHCI is halt.; EFI_TIMEOUT Failed to halt the controller before Timeout.

Halt the host controller.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Return values

EFI_SUCCESS	The EHCI is halt.
EFI_TIMEOUT	Failed to halt the controller before Timeout.

Definition at line 511 of file EhciReg.c.

◆ EhcInitHC()

EFI_STATUS EhcInitHC ( IN USB2_HC_DEV * Ehc )

Initialize the HC hardware. EHCI spec lists the five things to do to initialize the hardware:

Program CTRLDSSEGMENT
Set USBINTR to enable interrupts
Set periodic list base
Set USBCMD, interrupt threshold, frame list size etc
Write 1 to CONFIGFLAG to route all ports to EHCI

Parameters

Ehc	The EHCI device.

Returns: EFI_SUCCESS The EHCI has come out of halt state.; EFI_TIMEOUT Time out happened.

Definition at line 562 of file EhciReg.c.

◆ EhcIsDebugPortInUse()

BOOLEAN EhcIsDebugPortInUse	(	IN CONST USB2_HC_DEV *	Ehc,
		IN CONST UINT8 *PortNumber	OPTIONAL
	)

Check whether the host controller has an in-use debug port.

Parameters

[in]	Ehc	The Enhanced Host Controller to query.
[in]	PortNumber	If PortNumber is not NULL, then query whether PortNumber is an in-use debug port on Ehc. (PortNumber is taken in UEFI notation, i.e., zero-based.) Otherwise, query whether Ehc has any in-use debug port.

Return values

TRUE	PortNumber is an in-use debug port on Ehc (if PortNumber is not NULL), or some port on Ehc is an in-use debug port (otherwise).
FALSE	PortNumber is not an in-use debug port on Ehc (if PortNumber is not NULL), or no port on Ehc is an in-use debug port (otherwise).

Definition at line 104 of file EhciReg.c.

◆ EhcIsHalt()

BOOLEAN EhcIsHalt ( IN USB2_HC_DEV * Ehc )

Whether Ehc is halted.

Parameters

Ehc	The EHCI device.

Return values

TRUE	The controller is halted.
FALSE	It isn't halted.

Definition at line 442 of file EhciReg.c.

◆ EhcIsSysError()

BOOLEAN EhcIsSysError ( IN USB2_HC_DEV * Ehc )

Whether system error occurred.

Parameters

Ehc	The EHCI device.

Return values

TRUE	System error happened.
FALSE	No system error.

Whether system error occurred.

Parameters

Ehc	The EHCI device.

Returns: TRUE System error happened.; FALSE No system error.

Definition at line 459 of file EhciReg.c.

◆ EhcReadCapRegister()

UINT32 EhcReadCapRegister	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Offset
	)

Read EHCI capability register.

Parameters

Ehc	The EHCI device.
Offset	Capability register address.

Returns: The register content.

Read EHCI capability register.

Parameters

Ehc	The EHCI device.
Offset	Capability register address.

Returns: The register content read.

Return values

If	err, return 0xffff.

Definition at line 23 of file EhciReg.c.

◆ EhcReadOpReg()

UINT32 EhcReadOpReg	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Offset
	)

Read EHCI Operation register.

Parameters

Ehc	The EHCI device.
Offset	The operation register offset.

Returns: The register content.

Read EHCI Operation register.

Parameters

Ehc	The EHCI device.
Offset	The operation register offset.

Returns: The register content read.

Return values

If	err, return 0xffff.

Definition at line 147 of file EhciReg.c.

◆ EhcResetHC()

EFI_STATUS EhcResetHC	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Reset the host controller.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort (in millisecond, ms).

Return values

EFI_SUCCESS The host controller is reset.

Returns: Others Failed to reset the host.

Definition at line 477 of file EhciReg.c.

◆ EhcRunHC()

EFI_STATUS EhcRunHC	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Set the EHCI to run.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Returns: EFI_SUCCESS The EHCI is running.; Others Failed to set the EHCI to run.

Set the EHCI to run.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Return values

EFI_SUCCESS The EHCI is running.

Returns: Others Failed to set the EHCI to run.

Definition at line 534 of file EhciReg.c.

◆ EhcSetAndWaitDoorBell()

EFI_STATUS EhcSetAndWaitDoorBell	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Set door bell and wait it to be ACKed by host controller. This function is used to synchronize with the hardware.

Parameters

Ehc	The EHCI device.
Timeout	The time to wait before abort (in millisecond, ms).

Return values

EFI_SUCCESS	Synchronized with the hardware.
EFI_TIMEOUT	Time out happened while waiting door bell to set.

Definition at line 343 of file EhciReg.c.

◆ EhcSetOpRegBit()

VOID EhcSetOpRegBit	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Set one bit of the operational register while keeping other bits.

Parameters

Ehc	The EHCI device.
Offset	The offset of the operational register.
Bit	The bit mask of the register to set.

Definition at line 216 of file EhciReg.c.

◆ EhcWriteOpReg()

VOID EhcWriteOpReg	(	IN USB2_HC_DEV *	Ehc,
		IN UINT32	Offset,
		IN UINT32	Data
	)

Write the data to the EHCI operation register.

Parameters

Ehc	The EHCI device.
Offset	EHCI operation register offset.
Data	The data to write.

Definition at line 183 of file EhciReg.c.

Data Structures

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ CONFIGFLAG_ROUTE_EHC

◆ EHC_ADDR

◆ EHC_ASYNC_HEAD_OFFSET

◆ EHC_BAR_INDEX

◆ EHC_CAPLENGTH_OFFSET

◆ EHC_CONFIG_FLAG_OFFSET

◆ EHC_CTRLDSSEG_OFFSET

◆ EHC_DEBUG_PORT_CAP_ID

◆ EHC_FRAME_BASE_OFFSET

◆ EHC_FRAME_LEN

◆ EHC_FRINDEX_OFFSET

◆ EHC_HCCPARAMS_OFFSET

◆ EHC_HCSPARAMS_OFFSET

◆ EHC_LINK_TERMINATED

◆ EHC_PORT_STAT_OFFSET

◆ EHC_USBCMD_OFFSET

◆ EHC_USBINTR_OFFSET

◆ EHC_USBSTS_OFFSET

◆ EHCI_IS_DATAIN

◆ HCCP_64BIT

◆ HCSP_NPORTS

◆ HCSP_PPC

◆ PORSTSC_RESUME

◆ PORTSC_CHANGE_MASK

◆ PORTSC_CONN

◆ PORTSC_CONN_CHANGE

◆ PORTSC_ENABLE_CHANGE

◆ PORTSC_ENABLED

◆ PORTSC_LINESTATE_J

◆ PORTSC_LINESTATE_K

◆ PORTSC_OVERCUR

◆ PORTSC_OVERCUR_CHANGE

◆ PORTSC_OWNER

◆ PORTSC_POWER

◆ PORTSC_RESET

◆ PORTSC_SUSPEND

◆ USBCMD_ENABLE_ASYNC

◆ USBCMD_ENABLE_PERIOD

◆ USBCMD_IAAD

◆ USBCMD_RESET

◆ USBCMD_RUN

◆ USBSTS_ASYNC_ENABLED

◆ USBSTS_HALT

◆ USBSTS_IAA

◆ USBSTS_INTACK_MASK

◆ USBSTS_PERIOD_ENABLED

◆ USBSTS_SYS_ERROR

Function Documentation

◆ EhcAckAllInterrupt()

◆ EhcClearLegacySupport()

◆ EhcClearOpRegBit()

◆ EhcHaltHC()

◆ EhcInitHC()

◆ EhcIsDebugPortInUse()

◆ EhcIsHalt()

◆ EhcIsSysError()

◆ EhcReadCapRegister()

◆ EhcReadOpReg()

◆ EhcResetHC()

◆ EhcRunHC()

◆ EhcSetAndWaitDoorBell()

◆ EhcSetOpRegBit()

◆ EhcWriteOpReg()