Data Structures
struct	USB_PORT_STATE_MAP

struct	USB_CLASSC

Macros
#define	EHC_CAPLENGTH_OFFSET 0

#define	EHC_HCSPARAMS_OFFSET 0x04

#define	EHC_HCCPARAMS_OFFSET 0x08

#define	HCSP_NPORTS 0x0F

#define	HCCP_64BIT 0x01

#define	EHC_USBCMD_OFFSET 0x0

#define	EHC_USBSTS_OFFSET 0x04

#define	EHC_USBINTR_OFFSET 0x08

#define	EHC_FRINDEX_OFFSET 0x0C

#define	EHC_CTRLDSSEG_OFFSET 0x10

#define	EHC_FRAME_BASE_OFFSET 0x14

#define	EHC_ASYNC_HEAD_OFFSET 0x18

#define	EHC_CONFIG_FLAG_OFFSET 0x40

#define	EHC_PORT_STAT_OFFSET 0x44

#define	EHC_FRAME_LEN 1024

#define	CONFIGFLAG_ROUTE_EHC 0x01

#define	USBCMD_RUN 0x01

#define	USBCMD_RESET 0x02

#define	USBCMD_ENABLE_PERIOD 0x10

#define	USBCMD_ENABLE_ASYNC 0x20

#define	USBCMD_IAAD 0x40

#define	USBSTS_IAA 0x20

#define	USBSTS_PERIOD_ENABLED 0x4000

#define	USBSTS_ASYNC_ENABLED 0x8000

#define	USBSTS_HALT 0x1000

#define	USBSTS_SYS_ERROR 0x10

#define	USBSTS_INTACK_MASK 0x003F

#define	PORTSC_CONN 0x01

#define	PORTSC_CONN_CHANGE 0x02

#define	PORTSC_ENABLED 0x04

#define	PORTSC_ENABLE_CHANGE 0x08

#define	PORTSC_OVERCUR 0x10

#define	PORTSC_OVERCUR_CHANGE 0x20

#define	PORSTSC_RESUME 0x40

#define	PORTSC_SUSPEND 0x80

#define	PORTSC_RESET 0x100

#define	PORTSC_LINESTATE_K 0x400

#define	PORTSC_LINESTATE_J 0x800

#define	PORTSC_POWER 0x1000

#define	PORTSC_OWNER 0x2000

#define	PORTSC_CHANGE_MASK 0x2A

#define	EHC_BAR_INDEX 0

#define	EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)

#define	EHC_ADDR(High, QhHw32) ((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))

#define	EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)

Functions
UINT32	EhcReadCapRegister (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Offset)

UINT32	EhcReadOpReg (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Offset)

VOID	EhcWriteOpReg (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Offset, IN UINT32 Data)

VOID	EhcClearLegacySupport (IN PEI_USB2_HC_DEV *Ehc)

EFI_STATUS	EhcSetAndWaitDoorBell (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Timeout)

VOID	EhcAckAllInterrupt (IN PEI_USB2_HC_DEV *Ehc)

BOOLEAN	EhcIsHalt (IN PEI_USB2_HC_DEV *Ehc)

BOOLEAN	EhcIsSysError (IN PEI_USB2_HC_DEV *Ehc)

EFI_STATUS	EhcResetHC (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Timeout)

EFI_STATUS	EhcHaltHC (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Timeout)

EFI_STATUS	EhcRunHC (IN PEI_USB2_HC_DEV *Ehc, IN UINT32 Timeout)

EFI_STATUS	EhcInitHC (IN PEI_USB2_HC_DEV *Ehc)

Detailed Description

Private Header file for Usb Host Controller PEIM

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file EhciReg.h.

Macro Definition Documentation

◆ CONFIGFLAG_ROUTE_EHC

#define CONFIGFLAG_ROUTE_EHC 0x01

Definition at line 44 of file EhciReg.h.

◆ EHC_ADDR

#define EHC_ADDR	(	High,
		QhHw32
	)	((VOID *) (UINTN) (LShiftU64 ((High), 32) \| ((QhHw32) & 0xFFFFFFF0)))

Definition at line 82 of file EhciReg.h.

◆ EHC_ASYNC_HEAD_OFFSET

#define EHC_ASYNC_HEAD_OFFSET 0x18

Definition at line 35 of file EhciReg.h.

◆ EHC_BAR_INDEX

#define EHC_BAR_INDEX 0

Definition at line 78 of file EhciReg.h.

◆ EHC_CAPLENGTH_OFFSET

#define EHC_CAPLENGTH_OFFSET 0

Definition at line 16 of file EhciReg.h.

◆ EHC_CONFIG_FLAG_OFFSET

#define EHC_CONFIG_FLAG_OFFSET 0x40

Definition at line 36 of file EhciReg.h.

◆ EHC_CTRLDSSEG_OFFSET

#define EHC_CTRLDSSEG_OFFSET 0x10

Definition at line 33 of file EhciReg.h.

◆ EHC_FRAME_BASE_OFFSET

#define EHC_FRAME_BASE_OFFSET 0x14

Definition at line 34 of file EhciReg.h.

◆ EHC_FRAME_LEN

#define EHC_FRAME_LEN 1024

Definition at line 39 of file EhciReg.h.

◆ EHC_FRINDEX_OFFSET

#define EHC_FRINDEX_OFFSET 0x0C

Definition at line 32 of file EhciReg.h.

◆ EHC_HCCPARAMS_OFFSET

#define EHC_HCCPARAMS_OFFSET 0x08

Definition at line 18 of file EhciReg.h.

◆ EHC_HCSPARAMS_OFFSET

#define EHC_HCSPARAMS_OFFSET 0x04

Definition at line 17 of file EhciReg.h.

◆ EHC_LINK_TERMINATED

#define EHC_LINK_TERMINATED ( Link ) (((Link) & 0x01) != 0)

Definition at line 80 of file EhciReg.h.

◆ EHC_PORT_STAT_OFFSET

#define EHC_PORT_STAT_OFFSET 0x44

Definition at line 37 of file EhciReg.h.

◆ EHC_USBCMD_OFFSET

#define EHC_USBCMD_OFFSET 0x0

Definition at line 29 of file EhciReg.h.

◆ EHC_USBINTR_OFFSET

#define EHC_USBINTR_OFFSET 0x08

Definition at line 31 of file EhciReg.h.

◆ EHC_USBSTS_OFFSET

#define EHC_USBSTS_OFFSET 0x04

Definition at line 30 of file EhciReg.h.

◆ EHCI_IS_DATAIN

#define EHCI_IS_DATAIN ( EndpointAddr ) EHC_BIT_IS_SET((EndpointAddr), 0x80)

Definition at line 85 of file EhciReg.h.

◆ HCCP_64BIT

#define HCCP_64BIT 0x01

Definition at line 24 of file EhciReg.h.

◆ HCSP_NPORTS

#define HCSP_NPORTS 0x0F

Definition at line 23 of file EhciReg.h.

◆ PORSTSC_RESUME

#define PORSTSC_RESUME 0x40

Definition at line 66 of file EhciReg.h.

◆ PORTSC_CHANGE_MASK

#define PORTSC_CHANGE_MASK 0x2A

Definition at line 73 of file EhciReg.h.

◆ PORTSC_CONN

#define PORTSC_CONN 0x01

Definition at line 60 of file EhciReg.h.

◆ PORTSC_CONN_CHANGE

#define PORTSC_CONN_CHANGE 0x02

Definition at line 61 of file EhciReg.h.

◆ PORTSC_ENABLE_CHANGE

#define PORTSC_ENABLE_CHANGE 0x08

Definition at line 63 of file EhciReg.h.

◆ PORTSC_ENABLED

#define PORTSC_ENABLED 0x04

Definition at line 62 of file EhciReg.h.

◆ PORTSC_LINESTATE_J

#define PORTSC_LINESTATE_J 0x800

Definition at line 70 of file EhciReg.h.

◆ PORTSC_LINESTATE_K

#define PORTSC_LINESTATE_K 0x400

Definition at line 69 of file EhciReg.h.

◆ PORTSC_OVERCUR

#define PORTSC_OVERCUR 0x10

Definition at line 64 of file EhciReg.h.

◆ PORTSC_OVERCUR_CHANGE

#define PORTSC_OVERCUR_CHANGE 0x20

Definition at line 65 of file EhciReg.h.

◆ PORTSC_OWNER

#define PORTSC_OWNER 0x2000

Definition at line 72 of file EhciReg.h.

◆ PORTSC_POWER

#define PORTSC_POWER 0x1000

Definition at line 71 of file EhciReg.h.

◆ PORTSC_RESET

#define PORTSC_RESET 0x100

Definition at line 68 of file EhciReg.h.

◆ PORTSC_SUSPEND

#define PORTSC_SUSPEND 0x80

Definition at line 67 of file EhciReg.h.

◆ USBCMD_ENABLE_ASYNC

#define USBCMD_ENABLE_ASYNC 0x20

Definition at line 49 of file EhciReg.h.

◆ USBCMD_ENABLE_PERIOD

#define USBCMD_ENABLE_PERIOD 0x10

Definition at line 48 of file EhciReg.h.

◆ USBCMD_IAAD

#define USBCMD_IAAD 0x40

Definition at line 50 of file EhciReg.h.

◆ USBCMD_RESET

#define USBCMD_RESET 0x02

Definition at line 47 of file EhciReg.h.

◆ USBCMD_RUN

#define USBCMD_RUN 0x01

Definition at line 46 of file EhciReg.h.

◆ USBSTS_ASYNC_ENABLED

#define USBSTS_ASYNC_ENABLED 0x8000

Definition at line 54 of file EhciReg.h.

◆ USBSTS_HALT

#define USBSTS_HALT 0x1000

Definition at line 55 of file EhciReg.h.

◆ USBSTS_IAA

#define USBSTS_IAA 0x20

Definition at line 52 of file EhciReg.h.

◆ USBSTS_INTACK_MASK

#define USBSTS_INTACK_MASK 0x003F

Definition at line 57 of file EhciReg.h.

◆ USBSTS_PERIOD_ENABLED

#define USBSTS_PERIOD_ENABLED 0x4000

Definition at line 53 of file EhciReg.h.

◆ USBSTS_SYS_ERROR

#define USBSTS_SYS_ERROR 0x10

Definition at line 56 of file EhciReg.h.

Function Documentation

◆ EhcAckAllInterrupt()

VOID EhcAckAllInterrupt ( IN PEI_USB2_HC_DEV * Ehc )

Clear all the interrutp status bits, these bits are Write-Clean.

Parameters

Ehc	The EHCI device.

Definition at line 224 of file EhcPeim.c.

◆ EhcClearLegacySupport()

VOID EhcClearLegacySupport ( IN PEI_USB2_HC_DEV * Ehc )

Stop the legacy USB SMI support.

Parameters

Ehc	The EHCI device.

◆ EhcHaltHC()

EFI_STATUS EhcHaltHC	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Halt the host controller.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Return values

EFI_TIMEOUT	Failed to halt the controller before Timeout.
EFI_SUCCESS	The EHCI is halt.

Definition at line 359 of file EhcPeim.c.

◆ EhcInitHC()

EFI_STATUS EhcInitHC ( IN PEI_USB2_HC_DEV * Ehc )

Initialize the HC hardware. EHCI spec lists the five things to do to initialize the hardware.

Program CTRLDSSEGMENT.
Set USBINTR to enable interrupts.
Set periodic list base.
Set USBCMD, interrupt threshold, frame list size etc.
Write 1 to CONFIGFLAG to route all ports to EHCI.

Parameters

Ehc	The EHCI device.

Return values

EFI_SUCCESS	The EHCI has come out of halt state.
EFI_TIMEOUT	Time out happened.

Definition at line 438 of file EhcPeim.c.

◆ EhcIsHalt()

BOOLEAN EhcIsHalt ( IN PEI_USB2_HC_DEV * Ehc )

Check whether Ehc is halted.

Parameters

Ehc	The EHCI device.

Return values

TRUE	The controller is halted.
FALSE	The controller isn't halted.

Definition at line 290 of file EhcPeim.c.

◆ EhcIsSysError()

BOOLEAN EhcIsSysError ( IN PEI_USB2_HC_DEV * Ehc )

Check whether system error occurred.

Parameters

Ehc	The EHCI device.

Return values

TRUE	System error happened.
FALSE	No system error.

Definition at line 307 of file EhcPeim.c.

◆ EhcReadCapRegister()

UINT32 EhcReadCapRegister	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Offset
	)

Read EHCI capability register.

Parameters

Ehc	The EHCI device.
Offset	Capability register address.

Return values

the	register content read.

Definition at line 167 of file EhcPeim.c.

◆ EhcReadOpReg()

UINT32 EhcReadOpReg	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Offset
	)

Read Ehc Operation register.

Parameters

Ehc	The EHCI device.
Offset	The operation register offset.

Return values

the	register content read.

Definition at line 43 of file EhcPeim.c.

◆ EhcResetHC()

EFI_STATUS EhcResetHC	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Reset the host controller.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort (in millisecond, ms).

Return values

EFI_TIMEOUT	The transfer failed due to time out.
Others	Failed to reset the host.

Definition at line 325 of file EhcPeim.c.

◆ EhcRunHC()

EFI_STATUS EhcRunHC	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Set the EHCI to run

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Return values

EFI_SUCCESS	The EHCI is running.
Others	Failed to set the EHCI to run.

Set the EHCI to run.

Parameters

Ehc	The EHCI device.
Timeout	Time to wait before abort.

Return values

EFI_SUCCESS	The EHCI is running.
Others	Failed to set the EHCI to run.

Definition at line 382 of file EhcPeim.c.

◆ EhcSetAndWaitDoorBell()

EFI_STATUS EhcSetAndWaitDoorBell	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Timeout
	)

Set door bell and wait it to be ACKed by host controller. This function is used to synchronize with the hardware.

Parameters

Ehc	The EHCI device.
Timeout	The time to wait before abort (in millisecond, ms).

Return values

EFI_TIMEOUT	Time out happened while waiting door bell to set.
EFI_SUCCESS	Synchronized with the hardware.

Definition at line 191 of file EhcPeim.c.

◆ EhcWriteOpReg()

VOID EhcWriteOpReg	(	IN PEI_USB2_HC_DEV *	Ehc,
		IN UINT32	Offset,
		IN UINT32	Data
	)

Write the data to the EHCI operation register.

Parameters

Ehc	The EHCI device.
Offset	EHCI operation register offset.
Data	The data to write.

Definition at line 66 of file EhcPeim.c.

Data Structures

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ CONFIGFLAG_ROUTE_EHC

◆ EHC_ADDR

◆ EHC_ASYNC_HEAD_OFFSET

◆ EHC_BAR_INDEX

◆ EHC_CAPLENGTH_OFFSET

◆ EHC_CONFIG_FLAG_OFFSET

◆ EHC_CTRLDSSEG_OFFSET

◆ EHC_FRAME_BASE_OFFSET

◆ EHC_FRAME_LEN

◆ EHC_FRINDEX_OFFSET

◆ EHC_HCCPARAMS_OFFSET

◆ EHC_HCSPARAMS_OFFSET

◆ EHC_LINK_TERMINATED

◆ EHC_PORT_STAT_OFFSET

◆ EHC_USBCMD_OFFSET

◆ EHC_USBINTR_OFFSET

◆ EHC_USBSTS_OFFSET

◆ EHCI_IS_DATAIN

◆ HCCP_64BIT

◆ HCSP_NPORTS

◆ PORSTSC_RESUME

◆ PORTSC_CHANGE_MASK

◆ PORTSC_CONN

◆ PORTSC_CONN_CHANGE

◆ PORTSC_ENABLE_CHANGE

◆ PORTSC_ENABLED

◆ PORTSC_LINESTATE_J

◆ PORTSC_LINESTATE_K

◆ PORTSC_OVERCUR

◆ PORTSC_OVERCUR_CHANGE

◆ PORTSC_OWNER

◆ PORTSC_POWER

◆ PORTSC_RESET

◆ PORTSC_SUSPEND

◆ USBCMD_ENABLE_ASYNC

◆ USBCMD_ENABLE_PERIOD

◆ USBCMD_IAAD

◆ USBCMD_RESET

◆ USBCMD_RUN

◆ USBSTS_ASYNC_ENABLED

◆ USBSTS_HALT

◆ USBSTS_IAA

◆ USBSTS_INTACK_MASK

◆ USBSTS_PERIOD_ENABLED

◆ USBSTS_SYS_ERROR

Function Documentation

◆ EhcAckAllInterrupt()

◆ EhcClearLegacySupport()

◆ EhcHaltHC()

◆ EhcInitHC()

◆ EhcIsHalt()

◆ EhcIsSysError()

◆ EhcReadCapRegister()

◆ EhcReadOpReg()

◆ EhcResetHC()

◆ EhcRunHC()

◆ EhcSetAndWaitDoorBell()

◆ EhcWriteOpReg()