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Emmc.h
Go to the documentation of this file.
1
11#ifndef __EMMC_H__
12#define __EMMC_H__
13
14//
15// EMMC command index
16//
17#define EMMC_GO_IDLE_STATE 0
18#define EMMC_SEND_OP_COND 1
19#define EMMC_ALL_SEND_CID 2
20#define EMMC_SET_RELATIVE_ADDR 3
21#define EMMC_SET_DSR 4
22#define EMMC_SLEEP_AWAKE 5
23#define EMMC_SWITCH 6
24#define EMMC_SELECT_DESELECT_CARD 7
25#define EMMC_SEND_EXT_CSD 8
26#define EMMC_SEND_CSD 9
27#define EMMC_SEND_CID 10
28#define EMMC_STOP_TRANSMISSION 12
29#define EMMC_SEND_STATUS 13
30#define EMMC_BUSTEST_R 14
31#define EMMC_GO_INACTIVE_STATE 15
32#define EMMC_SET_BLOCKLEN 16
33#define EMMC_READ_SINGLE_BLOCK 17
34#define EMMC_READ_MULTIPLE_BLOCK 18
35#define EMMC_BUSTEST_W 19
36#define EMMC_SEND_TUNING_BLOCK 21
37#define EMMC_SET_BLOCK_COUNT 23
38#define EMMC_WRITE_BLOCK 24
39#define EMMC_WRITE_MULTIPLE_BLOCK 25
40#define EMMC_PROGRAM_CID 26
41#define EMMC_PROGRAM_CSD 27
42#define EMMC_SET_WRITE_PROT 28
43#define EMMC_CLR_WRITE_PROT 29
44#define EMMC_SEND_WRITE_PROT 30
45#define EMMC_SEND_WRITE_PROT_TYPE 31
46#define EMMC_ERASE_GROUP_START 35
47#define EMMC_ERASE_GROUP_END 36
48#define EMMC_ERASE 38
49#define EMMC_FAST_IO 39
50#define EMMC_GO_IRQ_STATE 40
51#define EMMC_LOCK_UNLOCK 42
52#define EMMC_SET_TIME 49
53#define EMMC_PROTOCOL_RD 53
54#define EMMC_PROTOCOL_WR 54
55#define EMMC_APP_CMD 55
56#define EMMC_GEN_CMD 56
57
58typedef enum {
59 EmmcPartitionUserData = 0,
60 EmmcPartitionBoot1 = 1,
61 EmmcPartitionBoot2 = 2,
62 EmmcPartitionRPMB = 3,
63 EmmcPartitionGP1 = 4,
64 EmmcPartitionGP2 = 5,
65 EmmcPartitionGP3 = 6,
66 EmmcPartitionGP4 = 7,
67 EmmcPartitionUnknown
68} EMMC_PARTITION_TYPE;
69
70#pragma pack(1)
71typedef struct {
72 UINT8 NotUsed : 1; // Not used [0:0]
73 UINT8 Crc : 7; // CRC [7:1]
74 UINT8 ManufacturingDate; // Manufacturing date [15:8]
75 UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
76 UINT8 ProductRevision; // Product revision [55:48]
77 UINT8 ProductName[6]; // Product name [103:56]
78 UINT8 OemId; // OEM/Application ID [111:104]
79 UINT8 DeviceType : 2; // Device/BGA [113:112]
80 UINT8 Reserved : 6; // Reserved [119:114]
81 UINT8 ManufacturerId; // Manufacturer ID [127:120]
82} EMMC_CID;
83
84typedef struct {
85 UINT32 NotUsed : 1; // Not used [0:0]
86 UINT32 Crc : 7; // CRC [7:1]
87 UINT32 Ecc : 2; // ECC code [9:8]
88 UINT32 FileFormat : 2; // File format [11:10]
89 UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]
90 UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]
91 UINT32 Copy : 1; // Copy flag (OTP) [14:14]
92 UINT32 FileFormatGrp : 1; // File format group [15:15]
93 UINT32 ContentProtApp : 1; // Content protection application [16:16]
94 UINT32 Reserved : 4; // Reserved [20:17]
95 UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]
96 UINT32 WriteBlLen : 4; // Max. write data block length [25:22]
97 UINT32 R2WFactor : 3; // Write speed factor [28:26]
98 UINT32 DefaultEcc : 2; // Manufacturer default ECC [30:29]
99 UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]
100
101 UINT32 WpGrpSize : 5; // Write protect group size [36:32]
102 UINT32 EraseGrpMult : 5; // Erase group size multiplier [41:37]
103 UINT32 EraseGrpSize : 5; // Erase group size [46:42]
104 UINT32 CSizeMult : 3; // Device size multiplier [49:47]
105 UINT32 VddWCurrMax : 3; // Max. write current @ VDD max [52:50]
106 UINT32 VddWCurrMin : 3; // Max. write current @ VDD min [55:53]
107 UINT32 VddRCurrMax : 3; // Max. read current @ VDD max [58:56]
108 UINT32 VddRCurrMin : 3; // Max. read current @ VDD min [61:59]
109 UINT32 CSizeLow : 2; // Device size low two bits [63:62]
110
111 UINT32 CSizeHigh : 10; // Device size high eight bits [73:64]
112 UINT32 Reserved1 : 2; // Reserved [75:74]
113 UINT32 DsrImp : 1; // DSR implemented [76:76]
114 UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]
115 UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]
116 UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]
117 UINT32 ReadBlLen : 4; // Max. read data block length [83:80]
118 UINT32 Ccc : 12; // Device command classes [95:84]
119
120 UINT32 TranSpeed : 8; // Max. bus clock frequency [103:96]
121 UINT32 Nsac : 8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
122 UINT32 Taac : 8; // Data read access-time 1 [119:112]
123 UINT32 Reserved2 : 2; // Reserved [121:120]
124 UINT32 SpecVers : 4; // System specification version [125:122]
125 UINT32 CsdStructure : 2; // CSD structure [127:126]
126} EMMC_CSD;
127
128typedef struct {
129 //
130 // Modes Segment
131 //
132 UINT8 Reserved[16]; // Reserved [15:0]
133 UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
134 UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
135 UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
136 UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
137 UINT8 FfuStatus; // FFU status R [26]
138 UINT8 Reserved1[2]; // Reserved [28:27]
139 UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
140 UINT8 ModeConfig; // Mode config R/W/EP [30]
141 UINT8 Reserved2; // Reserved [31]
142 UINT8 FlushCache; // Flushing of the cache W/EP [32]
143 UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
144 UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
145 UINT8 PackedFailureIndex; // Packed command failure index R [35]
146 UINT8 PackedCommandStatus; // Packed command status R [36]
147 UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
148 UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
149 UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
150 UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
151 UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
152 UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
153 UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
154 UINT8 DataSectorSize; // Sector size R [61]
155 UINT8 UseNativeSector; // Sector size emulation R/W [62]
156 UINT8 NativeSectorSize; // Native sector size R [63]
157 UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]
158 UINT8 Reserved3[2]; // Reserved [129:128]
159 UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
160 UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
161 UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
162 UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
163 UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
164 UINT8 Reserved4; // Reserved [135]
165 UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
166 UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
167 UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
168 UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
169 UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
170 UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
171 UINT8 PartitioningSupport; // Partitioning Support R [160]
172 UINT8 HpiMgmt; // HPI management R/W/EP [161]
173 UINT8 RstFunction; // H/W reset function R/W [162]
174 UINT8 BkopsEn; // Enable background operations handshake R/W [163]
175 UINT8 BkopsStart; // Manually start background operations W/EP [164]
176 UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
177 UINT8 WrRelParam; // Write reliability parameter register R [166]
178 UINT8 WrRelSet; // Write reliability setting register R/W [167]
179 UINT8 RpmbSizeMult; // RPMB Size R [168]
180 UINT8 FwConfig; // FW configuration R/W [169]
181 UINT8 Reserved5; // Reserved [170]
182 UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
183 UINT8 Reserved6; // Reserved [172]
184 UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
185 UINT8 BootWpStatus; // Boot write protection status registers R [174]
186 UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
187 UINT8 Reserved7; // Reserved [176]
188 UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
189 UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
190 UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
191 UINT8 Reserved8; // Reserved [180]
192 UINT8 ErasedMemCont; // Erased memory content R [181]
193 UINT8 Reserved9; // Reserved [182]
194 UINT8 BusWidth; // Bus width mode W/EP [183]
195 UINT8 Reserved10; // Reserved [184]
196 UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
197 UINT8 Reserved11; // Reserved [186]
198 UINT8 PowerClass; // Power class R/W/EP [187]
199 UINT8 Reserved12; // Reserved [188]
200 UINT8 CmdSetRev; // Command set revision R [189]
201 UINT8 Reserved13; // Reserved [190]
202 UINT8 CmdSet; // Command set R/W/EP [191]
203 //
204 // Properties Segment
205 //
206 UINT8 ExtCsdRev; // Extended CSD revision [192]
207 UINT8 Reserved14; // Reserved [193]
208 UINT8 CsdStructure; // CSD STRUCTURE [194]
209 UINT8 Reserved15; // Reserved [195]
210 UINT8 DeviceType; // Device type [196]
211 UINT8 DriverStrength; // I/O Driver Strength [197]
212 UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
213 UINT8 PartitionSwitchTime; // Partition switching timing [199]
214 UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
215 UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
216 UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
217 UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
218 UINT8 Reserved16; // Reserved [204]
219 UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
220 UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
221 UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
222 UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
223 UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
224 UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
225 UINT8 Reserved17; // Reserved [211]
226 UINT8 SecCount[4]; // Sector Count [215:212]
227 UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]
228 UINT8 SATimeout; // Sleep/awake timeout [217]
229 UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
230 UINT8 SCVccq; // Sleep current (VCCQ) [219]
231 UINT8 SCVcc; // Sleep current (VCC) [220]
232 UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
233 UINT8 RelWrSecC; // Reliable write sector count [222]
234 UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
235 UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
236 UINT8 AccSize; // Access size [225]
237 UINT8 BootSizeMult; // Boot partition size [226]
238 UINT8 Reserved18; // Reserved [227]
239 UINT8 BootInfo; // Boot information [228]
240 UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
241 UINT8 SecEraseMult; // Secure Erase Multiplier [230]
242 UINT8 SecFeatureSupport; // Secure Feature support [231]
243 UINT8 TrimMult; // TRIM Multiplier [232]
244 UINT8 Reserved19; // Reserved [233]
245 UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
246 UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
247 UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
248 UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
249 UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
250 UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
251 UINT8 Reserved20; // Reserved [240]
252 UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
253 UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
254 UINT8 BkopsStatus; // Background operations status [246]
255 UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
256 UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
257 UINT8 CacheSize[4]; // Cache size [252:249]
258 UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
259 UINT8 FirmwareVersion[8]; // Firmware version [261:254]
260 UINT8 DeviceVersion[2]; // Device version [263:262]
261 UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
262 UINT8 OptimalWriteSize; // Optimal write size [265]
263 UINT8 OptimalReadSize; // Optimal read size [266]
264 UINT8 PreEolInfo; // Pre EOL information [267]
265 UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
266 UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
267 UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
268 UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
269 UINT8 Reserved21[181]; // Reserved [486:306]
270 UINT8 FfuArg[4]; // FFU Argument [490:487]
271 UINT8 OperationCodeTimeout; // Operation codes timeout [491]
272 UINT8 FfuFeatures; // FFU features [492]
273 UINT8 SupportedModes; // Supported modes [493]
274 UINT8 ExtSupport; // Extended partitions attribute support [494]
275 UINT8 LargeUnitSizeM1; // Large Unit size [495]
276 UINT8 ContextCapabilities; // Context management capabilities [496]
277 UINT8 TagResSize; // Tag Resources Size [497]
278 UINT8 TagUnitSize; // Tag Unit Size [498]
279 UINT8 DataTagSupport; // Data Tag Support [499]
280 UINT8 MaxPackedWrites; // Max packed write commands [500]
281 UINT8 MaxPackedReads; // Max packed read commands[501]
282 UINT8 BkOpsSupport; // Background operations support [502]
283 UINT8 HpiFeatures; // HPI features [503]
284 UINT8 SupportedCmdSet; // Supported Command Sets [504]
285 UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
286 UINT8 Reserved22[6]; // Reserved [511:506]
287} EMMC_EXT_CSD;
288
289#pragma pack()
290
291#endif
EMMC_CID
Definition: Emmc.h:71
EMMC_CSD
Definition: Emmc.h:84
EMMC_EXT_CSD
Definition: Emmc.h:128