TianoCore EDK2 master
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FlushCacheLine.c
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1
24VOID *
25EFIAPI
27 IN VOID *LinearAddress
28 )
29{
30 //
31 // If the CPU does not support CLFLUSH instruction,
32 // then promote flush range to flush entire cache.
33 //
34 _asm {
35 mov eax, 1
36 cpuid
37 test edx, BIT19
38 jz NoClflush
39 mov eax, dword ptr [LinearAddress]
40 clflush [eax]
41 jmp Done
42NoClflush:
43 wbinvd
44Done:
45 }
46
47 return LinearAddress;
48}
VOID *EFIAPI AsmFlushCacheLine(IN VOID *LinearAddress)
#define IN
Definition: Base.h:279