TianoCore EDK2 master
Ghcb.h
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1
15#ifndef __GHCB_H__
16#define __GHCB_H__
17
18#include <Base.h>
19#include <Library/BaseLib.h>
20#include <Library/DebugLib.h>
21
22#define UD_EXCEPTION 6
23#define GP_EXCEPTION 13
24#define VC_EXCEPTION 29
25
26#define GHCB_VERSION_MIN 1
27#define GHCB_VERSION_MAX 2
28
29#define GHCB_STANDARD_USAGE 0
30
31//
32// SVM Exit Codes
33//
34#define SVM_EXIT_DR7_READ 0x27ULL
35#define SVM_EXIT_DR7_WRITE 0x37ULL
36#define SVM_EXIT_RDTSC 0x6EULL
37#define SVM_EXIT_RDPMC 0x6FULL
38#define SVM_EXIT_CPUID 0x72ULL
39#define SVM_EXIT_INVD 0x76ULL
40#define SVM_EXIT_IOIO_PROT 0x7BULL
41#define SVM_EXIT_MSR 0x7CULL
42#define SVM_EXIT_VMMCALL 0x81ULL
43#define SVM_EXIT_RDTSCP 0x87ULL
44#define SVM_EXIT_WBINVD 0x89ULL
45#define SVM_EXIT_MONITOR 0x8AULL
46#define SVM_EXIT_MWAIT 0x8BULL
47#define SVM_EXIT_NPF 0x400ULL
48
49//
50// VMG Special Exit Codes
51//
52#define SVM_EXIT_MMIO_READ 0x80000001ULL
53#define SVM_EXIT_MMIO_WRITE 0x80000002ULL
54#define SVM_EXIT_NMI_COMPLETE 0x80000003ULL
55#define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL
56#define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL
57#define SVM_EXIT_SNP_PAGE_STATE_CHANGE 0x80000010ULL
58#define SVM_EXIT_SNP_AP_CREATION 0x80000013ULL
59#define SVM_EXIT_HYPERVISOR_FEATURES 0x8000FFFDULL
60#define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL
61
62//
63// IOIO Exit Information
64//
65#define IOIO_TYPE_STR BIT2
66#define IOIO_TYPE_IN 1
67#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR)
68#define IOIO_TYPE_OUT 0
69#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR)
70
71#define IOIO_REP BIT3
72
73#define IOIO_ADDR_64 BIT9
74#define IOIO_ADDR_32 BIT8
75#define IOIO_ADDR_16 BIT7
76
77#define IOIO_DATA_32 BIT6
78#define IOIO_DATA_16 BIT5
79#define IOIO_DATA_8 BIT4
80#define IOIO_DATA_MASK (BIT6 | BIT5 | BIT4)
81#define IOIO_DATA_OFFSET 4
82#define IOIO_DATA_BYTES(x) (((x) & IOIO_DATA_MASK) >> IOIO_DATA_OFFSET)
83
84#define IOIO_SEG_ES 0
85#define IOIO_SEG_DS (BIT11 | BIT10)
86
87//
88// AP Creation Information
89//
90#define SVM_VMGEXIT_SNP_AP_CREATE_ON_INIT 0
91#define SVM_VMGEXIT_SNP_AP_CREATE 1
92#define SVM_VMGEXIT_SNP_AP_DESTROY 2
93
94typedef PACKED struct {
95 UINT8 Reserved1[203];
96 UINT8 Cpl;
97 UINT8 Reserved8[300];
98 UINT64 Rax;
99 UINT8 Reserved4[264];
100 UINT64 Rcx;
101 UINT64 Rdx;
102 UINT64 Rbx;
103 UINT8 Reserved5[112];
104 UINT64 SwExitCode;
105 UINT64 SwExitInfo1;
106 UINT64 SwExitInfo2;
107 UINT64 SwScratch;
108 UINT8 Reserved6[56];
109 UINT64 XCr0;
110 UINT8 ValidBitmap[16];
111 UINT64 X87StateGpa;
112 UINT8 Reserved7[1016];
113} GHCB_SAVE_AREA;
114
115typedef PACKED struct {
116 GHCB_SAVE_AREA SaveArea;
117 UINT8 SharedBuffer[2032];
118 UINT8 Reserved1[10];
119 UINT16 ProtocolVersion;
120 UINT32 GhcbUsage;
121} GHCB;
122
123#define GHCB_SAVE_AREA_QWORD_OFFSET(RegisterField) \
124 (OFFSET_OF (GHCB, SaveArea.RegisterField) / sizeof (UINT64))
125
126typedef enum {
127 GhcbCpl = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl),
128 GhcbRax = GHCB_SAVE_AREA_QWORD_OFFSET (Rax),
129 GhcbRbx = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx),
130 GhcbRcx = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx),
131 GhcbRdx = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx),
132 GhcbXCr0 = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0),
133 GhcbSwExitCode = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode),
134 GhcbSwExitInfo1 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1),
135 GhcbSwExitInfo2 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2),
136 GhcbSwScratch = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch),
137} GHCB_REGISTER;
138
139typedef union {
140 struct {
141 UINT32 Lower32Bits;
142 UINT32 Upper32Bits;
143 } Elements;
144
145 UINT64 Uint64;
147
148typedef union {
149 struct {
150 UINT32 Vector : 8;
151 UINT32 Type : 3;
152 UINT32 ErrorCodeValid : 1;
153 UINT32 Rsvd : 19;
154 UINT32 Valid : 1;
155 UINT32 ErrorCode;
156 } Elements;
157
158 UINT64 Uint64;
160
161#define GHCB_EVENT_INJECTION_TYPE_INT 0
162#define GHCB_EVENT_INJECTION_TYPE_NMI 2
163#define GHCB_EVENT_INJECTION_TYPE_EXCEPTION 3
164#define GHCB_EVENT_INJECTION_TYPE_SOFT_INT 4
165
166//
167// Hypervisor features
168//
169#define GHCB_HV_FEATURES_SNP BIT0
170#define GHCB_HV_FEATURES_SNP_AP_CREATE (GHCB_HV_FEATURES_SNP | BIT1)
171#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)
172#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)
173
174//
175// SNP Page State Change.
176//
177// Note that the PSMASH and UNSMASH operations are not supported when using the MSR protocol.
178//
179#define SNP_PAGE_STATE_PRIVATE 1
180#define SNP_PAGE_STATE_SHARED 2
181#define SNP_PAGE_STATE_PSMASH 3
182#define SNP_PAGE_STATE_UNSMASH 4
183
184typedef struct {
185 UINT64 CurrentPage : 12;
186 UINT64 GuestFrameNumber : 40;
187 UINT64 Operation : 4;
188 UINT64 PageSize : 1;
189 UINT64 Reserved : 7;
191
192typedef struct {
193 UINT16 CurrentEntry;
194 UINT16 EndEntry;
195 UINT32 Reserved;
197
198#define SNP_PAGE_STATE_MAX_ENTRY 253
199
200typedef struct {
202 SNP_PAGE_STATE_ENTRY Entry[SNP_PAGE_STATE_MAX_ENTRY];
204
205//
206// SEV-ES save area mapping structures used for SEV-SNP AP Creation.
207// Only the fields required to be set to a non-zero value are defined.
208//
209// The segment register definition is defined for processor reset/real mode
210// (as when an INIT of the vCPU is requested). Should other modes (long mode,
211// etc.) be required, then the definitions can be enhanced.
212//
213
214//
215// Segment types at processor reset, See AMD APM Volume 2, Table 14-2.
216//
217#define SEV_ES_RESET_CODE_SEGMENT_TYPE 0xA
218#define SEV_ES_RESET_DATA_SEGMENT_TYPE 0x2
219
220#define SEV_ES_RESET_LDT_TYPE 0x2
221#define SEV_ES_RESET_TSS_TYPE 0x3
222
223#pragma pack (1)
224typedef union {
225 struct {
226 UINT16 Type : 4;
227 UINT16 Sbit : 1;
228 UINT16 Dpl : 2;
229 UINT16 Present : 1;
230 UINT16 Avl : 1;
231 UINT16 Reserved1 : 1;
232 UINT16 Db : 1;
233 UINT16 Granularity : 1;
234 } Bits;
235 UINT16 Uint16;
237
238typedef struct {
239 UINT16 Selector;
241 UINT32 Limit;
242 UINT64 Base;
244
245typedef struct {
256 UINT8 Reserved1[42];
257 UINT8 Vmpl;
258 UINT8 Reserved2[5];
259 UINT64 Efer;
260 UINT8 Reserved3[112];
261 UINT64 Cr4;
262 UINT8 Reserved4[8];
263 UINT64 Cr0;
264 UINT64 Dr7;
265 UINT64 Dr6;
266 UINT64 Rflags;
267 UINT64 Rip;
268 UINT8 Reserved5[232];
269 UINT64 GPat;
270 UINT8 Reserved6[320];
271 UINT64 SevFeatures;
272 UINT8 Reserved7[48];
273 UINT64 XCr0;
274 UINT8 Reserved8[24];
275 UINT32 Mxcsr;
276 UINT16 X87Ftw;
277 UINT8 Reserved9[2];
278 UINT16 X87Fcw;
280#pragma pack ()
281
282#endif