TianoCore EDK2 master
HaswellMsr.h
Go to the documentation of this file.
1
18#ifndef __HASWELL_MSR_H__
19#define __HASWELL_MSR_H__
20
22
32#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x3C || \
36 DisplayModel == 0x45 || \
37 DisplayModel == 0x46 \
38 ) \
39 )
40
59#define MSR_HASWELL_PLATFORM_INFO 0x000000CE
60
64typedef union {
68 struct {
69 UINT32 Reserved1 : 8;
76 UINT32 Reserved2 : 12;
83 UINT32 RatioLimit : 1;
90 UINT32 TDPLimit : 1;
91 UINT32 Reserved3 : 2;
103 UINT32 ConfigTDPLevels : 2;
104 UINT32 Reserved4 : 5;
116 UINT32 Reserved5 : 8;
117 } Bits;
121 UINT64 Uint64;
123
146#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186
147#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187
148#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189
150
155typedef union {
159 struct {
163 UINT32 EventSelect : 8;
168 UINT32 UMASK : 8;
172 UINT32 USR : 1;
176 UINT32 OS : 1;
180 UINT32 E : 1;
184 UINT32 PC : 1;
188 UINT32 INT : 1;
196 UINT32 ANY : 1;
201 UINT32 EN : 1;
205 UINT32 INV : 1;
211 UINT32 CMASK : 8;
212 UINT32 Reserved : 32;
217 UINT32 IN_TX : 1;
218 UINT32 Reserved2 : 31;
219 } Bits;
223 UINT64 Uint64;
225
245#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188
246
250typedef union {
254 struct {
258 UINT32 EventSelect : 8;
263 UINT32 UMASK : 8;
267 UINT32 USR : 1;
271 UINT32 OS : 1;
275 UINT32 E : 1;
279 UINT32 PC : 1;
283 UINT32 INT : 1;
291 UINT32 ANY : 1;
296 UINT32 EN : 1;
300 UINT32 INV : 1;
306 UINT32 CMASK : 8;
307 UINT32 Reserved : 32;
312 UINT32 IN_TX : 1;
322 UINT32 IN_TXCP : 1;
323 UINT32 Reserved2 : 30;
324 } Bits;
328 UINT64 Uint64;
330
349#define MSR_HASWELL_LBR_SELECT 0x000001C8
350
354typedef union {
358 struct {
362 UINT32 CPL_EQ_0 : 1;
366 UINT32 CPL_NEQ_0 : 1;
370 UINT32 JCC : 1;
374 UINT32 NEAR_REL_CALL : 1;
378 UINT32 NEAR_IND_CALL : 1;
382 UINT32 NEAR_RET : 1;
386 UINT32 NEAR_IND_JMP : 1;
390 UINT32 NEAR_REL_JMP : 1;
394 UINT32 FAR_BRANCH : 1;
398 UINT32 EN_CALL_STACK : 1;
399 UINT32 Reserved1 : 22;
400 UINT32 Reserved2 : 32;
401 } Bits;
405 UINT32 Uint32;
409 UINT64 Uint64;
411
435#define MSR_HASWELL_PKGC_IRTL1 0x0000060B
436
440typedef union {
444 struct {
456 UINT32 TimeUnit : 3;
457 UINT32 Reserved1 : 2;
462 UINT32 Valid : 1;
463 UINT32 Reserved2 : 16;
464 UINT32 Reserved3 : 32;
465 } Bits;
469 UINT32 Uint32;
473 UINT64 Uint64;
475
499#define MSR_HASWELL_PKGC_IRTL2 0x0000060C
500
504typedef union {
508 struct {
520 UINT32 TimeUnit : 3;
521 UINT32 Reserved1 : 2;
526 UINT32 Valid : 1;
527 UINT32 Reserved2 : 16;
528 UINT32 Reserved3 : 32;
529 } Bits;
533 UINT32 Uint32;
537 UINT64 Uint64;
539
555#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613
556
572#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619
573
590#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B
591
609#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648
610
614typedef union {
618 struct {
623 UINT32 Config_TDP_Base : 8;
624 UINT32 Reserved1 : 24;
625 UINT32 Reserved2 : 32;
626 } Bits;
630 UINT32 Uint32;
634 UINT64 Uint64;
636
654#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649
655
659typedef union {
663 struct {
667 UINT32 PKG_TDP_LVL1 : 15;
668 UINT32 Reserved1 : 1;
674 UINT32 Reserved2 : 8;
679 UINT32 PKG_MAX_PWR_LVL1 : 15;
684 UINT32 PKG_MIN_PWR_LVL1 : 16;
685 UINT32 Reserved3 : 1;
686 } Bits;
690 UINT64 Uint64;
692
710#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A
711
715typedef union {
719 struct {
723 UINT32 PKG_TDP_LVL2 : 15;
724 UINT32 Reserved1 : 1;
730 UINT32 Reserved2 : 8;
735 UINT32 PKG_MAX_PWR_LVL2 : 15;
740 UINT32 PKG_MIN_PWR_LVL2 : 16;
741 UINT32 Reserved3 : 1;
742 } Bits;
746 UINT64 Uint64;
748
767#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B
768
772typedef union {
776 struct {
780 UINT32 TDP_LEVEL : 2;
781 UINT32 Reserved1 : 29;
786 UINT32 Config_TDP_Lock : 1;
787 UINT32 Reserved2 : 32;
788 } Bits;
792 UINT32 Uint32;
796 UINT64 Uint64;
798
817#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C
818
822typedef union {
826 struct {
832 UINT32 Reserved1 : 23;
838 UINT32 Reserved2 : 32;
839 } Bits;
843 UINT32 Uint32;
847 UINT64 Uint64;
849
870#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
871
875typedef union {
879 struct {
889 UINT32 Limit : 4;
890 UINT32 Reserved1 : 6;
894 UINT32 IO_MWAIT : 1;
895 UINT32 Reserved2 : 4;
899 UINT32 CFGLock : 1;
900 UINT32 Reserved3 : 9;
904 UINT32 C3AutoDemotion : 1;
908 UINT32 C1AutoDemotion : 1;
912 UINT32 C3Undemotion : 1;
916 UINT32 C1Undemotion : 1;
917 UINT32 Reserved4 : 3;
918 UINT32 Reserved5 : 32;
919 } Bits;
923 UINT32 Uint32;
927 UINT64 Uint64;
929
949#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D
950
954typedef union {
958 struct {
959 UINT32 Reserved1 : 32;
960 UINT32 Reserved2 : 26;
973 UINT32 Reserved3 : 4;
974 } Bits;
978 UINT64 Uint64;
980
999#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD
1000
1004typedef union {
1008 struct {
1013 UINT32 Maximum1C : 8;
1018 UINT32 Maximum2C : 8;
1023 UINT32 Maximum3C : 8;
1028 UINT32 Maximum4C : 8;
1029 UINT32 Reserved : 32;
1030 } Bits;
1034 UINT32 Uint32;
1038 UINT64 Uint64;
1040
1059#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391
1060
1064typedef union {
1068 struct {
1072 UINT32 PMI_Sel_Core0 : 1;
1076 UINT32 PMI_Sel_Core1 : 1;
1080 UINT32 PMI_Sel_Core2 : 1;
1084 UINT32 PMI_Sel_Core3 : 1;
1085 UINT32 Reserved1 : 15;
1086 UINT32 Reserved2 : 10;
1090 UINT32 EN : 1;
1094 UINT32 WakePMI : 1;
1098 UINT32 FREEZE : 1;
1099 UINT32 Reserved3 : 32;
1100 } Bits;
1104 UINT32 Uint32;
1108 UINT64 Uint64;
1110
1129#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392
1130
1134typedef union {
1138 struct {
1142 UINT32 Fixed : 1;
1146 UINT32 ARB : 1;
1147 UINT32 Reserved1 : 1;
1151 UINT32 CBox : 1;
1152 UINT32 Reserved2 : 28;
1153 UINT32 Reserved3 : 32;
1154 } Bits;
1158 UINT32 Uint32;
1162 UINT64 Uint64;
1164
1183#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394
1184
1188typedef union {
1192 struct {
1193 UINT32 Reserved1 : 20;
1197 UINT32 EnableOverflow : 1;
1198 UINT32 Reserved2 : 1;
1202 UINT32 EnableCounting : 1;
1203 UINT32 Reserved3 : 9;
1204 UINT32 Reserved4 : 32;
1205 } Bits;
1209 UINT32 Uint32;
1213 UINT64 Uint64;
1215
1234#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395
1235
1239typedef union {
1243 struct {
1247 UINT32 CurrentCount : 32;
1251 UINT32 CurrentCountHi : 16;
1252 UINT32 Reserved : 16;
1253 } Bits;
1257 UINT64 Uint64;
1259
1277#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396
1278
1282typedef union {
1286 struct {
1290 UINT32 CBox : 4;
1291 UINT32 Reserved1 : 28;
1292 UINT32 Reserved2 : 32;
1293 } Bits;
1297 UINT32 Uint32;
1301 UINT64 Uint64;
1303
1320#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0
1321
1338#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1
1339
1356#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2
1357
1374#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3
1375
1395#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0
1396
1400typedef union {
1404 struct {
1409 UINT32 Lock : 1;
1410 UINT32 Reserved1 : 1;
1420 UINT32 Reserved2 : 29;
1421 UINT32 Reserved3 : 32;
1422 } Bits;
1426 UINT32 Uint32;
1430 UINT64 Uint64;
1432
1468#define MSR_HASWELL_SMM_DELAYED 0x000004E2
1469
1501#define MSR_HASWELL_SMM_BLOCKED 0x000004E3
1502
1520#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606
1521
1525typedef union {
1529 struct {
1533 UINT32 PowerUnits : 4;
1534 UINT32 Reserved1 : 4;
1542 UINT32 Reserved2 : 3;
1547 UINT32 TimeUnits : 4;
1548 UINT32 Reserved3 : 12;
1549 UINT32 Reserved4 : 32;
1550 } Bits;
1554 UINT32 Uint32;
1558 UINT64 Uint64;
1560
1577#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639
1578
1596#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640
1597
1614#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641
1615
1633#define MSR_HASWELL_PP1_POLICY 0x00000642
1634
1654#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690
1655
1659typedef union {
1663 struct {
1669 UINT32 PROCHOT_Status : 1;
1674 UINT32 ThermalStatus : 1;
1675 UINT32 Reserved1 : 2;
1694 UINT32 Reserved2 : 1;
1705 UINT32 PLStatus : 1;
1711 UINT32 PL1Status : 1;
1717 UINT32 PL2Status : 1;
1730 UINT32 Reserved3 : 2;
1736 UINT32 PROCHOT_Log : 1;
1742 UINT32 ThermalLog : 1;
1743 UINT32 Reserved4 : 2;
1763 UINT32 Reserved5 : 1;
1776 UINT32 PLLog : 1;
1783 UINT32 PL1Log : 1;
1790 UINT32 PL2Log : 1;
1804 UINT32 Reserved6 : 2;
1805 UINT32 Reserved7 : 32;
1806 } Bits;
1810 UINT32 Uint32;
1814 UINT64 Uint64;
1816
1836#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1837
1842typedef union {
1846 struct {
1851 UINT32 PROCHOT_Status : 1;
1856 UINT32 ThermalStatus : 1;
1857 UINT32 Reserved1 : 2;
1876 UINT32 Reserved2 : 1;
1894 UINT32 PL1STatus : 1;
1900 UINT32 PL2Status : 1;
1901 UINT32 Reserved3 : 4;
1907 UINT32 PROCHOT_Log : 1;
1913 UINT32 ThermalLog : 1;
1914 UINT32 Reserved4 : 2;
1934 UINT32 Reserved5 : 1;
1954 UINT32 PL1Log : 1;
1961 UINT32 PL2Log : 1;
1975 UINT32 Reserved6 : 2;
1976 UINT32 Reserved7 : 32;
1977 } Bits;
1981 UINT32 Uint32;
1985 UINT64 Uint64;
1987
2007#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1
2008
2012typedef union {
2016 struct {
2021 UINT32 PROCHOT_Status : 1;
2026 UINT32 ThermalStatus : 1;
2027 UINT32 Reserved1 : 4;
2034 UINT32 Reserved2 : 1;
2041 UINT32 Reserved3 : 1;
2047 UINT32 PL1STatus : 1;
2053 UINT32 PL2Status : 1;
2054 UINT32 Reserved4 : 4;
2060 UINT32 PROCHOT_Log : 1;
2066 UINT32 ThermalLog : 1;
2067 UINT32 Reserved5 : 2;
2087 UINT32 Reserved6 : 1;
2107 UINT32 PL1Log : 1;
2114 UINT32 PL2Log : 1;
2128 UINT32 Reserved7 : 2;
2129 UINT32 Reserved8 : 32;
2130 } Bits;
2134 UINT32 Uint32;
2138 UINT64 Uint64;
2140
2157#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700
2158
2175#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701
2176
2193#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706
2194
2211#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707
2212
2229#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710
2230
2247#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711
2248
2265#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716
2266
2283#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717
2284
2301#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720
2302
2319#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721
2320
2337#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726
2338
2355#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727
2356
2373#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730
2374
2391#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731
2392
2409#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736
2410
2427#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737
2428
2448#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630
2449
2453typedef union {
2457 struct {
2470 UINT32 Reserved : 4;
2471 } Bits;
2475 UINT64 Uint64;
2477
2497#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631
2498
2502typedef union {
2506 struct {
2519 UINT32 Reserved : 4;
2520 } Bits;
2524 UINT64 Uint64;
2526
2546#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632
2547
2551typedef union {
2555 struct {
2568 UINT32 Reserved : 4;
2569 } Bits;
2573 UINT64 Uint64;
2575
2576#endif