HaswellMsr.h

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#ifndef __HASWELL_MSR_H__
#define __HASWELL_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x3C || \
    DisplayModel == 0x45 || \
    DisplayModel == 0x46    \
    )                       \
   )
 
#define MSR_HASWELL_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNonTurboRatio   : 8;
    UINT32    Reserved2              : 12;
    UINT32    RatioLimit             : 1;
    UINT32    TDPLimit               : 1;
    UINT32    Reserved3              : 2;
    UINT32    LowPowerModeSupport    : 1;
    UINT32    ConfigTDPLevels        : 2;
    UINT32    Reserved4              : 5;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    MinimumOperatingRatio  : 8;
    UINT32    Reserved5              : 8;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_PLATFORM_INFO_REGISTER;
 
#define MSR_HASWELL_IA32_PERFEVTSEL0  0x00000186
#define MSR_HASWELL_IA32_PERFEVTSEL1  0x00000187
#define MSR_HASWELL_IA32_PERFEVTSEL3  0x00000189
 
typedef union {
  struct {
    UINT32    EventSelect : 8;
    UINT32    UMASK       : 8;
    UINT32    USR         : 1;
    UINT32    OS          : 1;
    UINT32    E           : 1;
    UINT32    PC          : 1;
    UINT32    INT         : 1;
    UINT32    ANY         : 1;
    UINT32    EN          : 1;
    UINT32    INV         : 1;
    UINT32    CMASK       : 8;
    UINT32    Reserved    : 32;
    UINT32    IN_TX       : 1;
    UINT32    Reserved2   : 31;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;
 
#define MSR_HASWELL_IA32_PERFEVTSEL2  0x00000188
 
typedef union {
  struct {
    UINT32    EventSelect : 8;
    UINT32    UMASK       : 8;
    UINT32    USR         : 1;
    UINT32    OS          : 1;
    UINT32    E           : 1;
    UINT32    PC          : 1;
    UINT32    INT         : 1;
    UINT32    ANY         : 1;
    UINT32    EN          : 1;
    UINT32    INV         : 1;
    UINT32    CMASK       : 8;
    UINT32    Reserved    : 32;
    UINT32    IN_TX       : 1;
    UINT32    IN_TXCP   : 1;
    UINT32    Reserved2 : 30;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;
 
#define MSR_HASWELL_LBR_SELECT  0x000001C8
 
typedef union {
  struct {
    UINT32    CPL_EQ_0      : 1;
    UINT32    CPL_NEQ_0     : 1;
    UINT32    JCC           : 1;
    UINT32    NEAR_REL_CALL : 1;
    UINT32    NEAR_IND_CALL : 1;
    UINT32    NEAR_RET      : 1;
    UINT32    NEAR_IND_JMP  : 1;
    UINT32    NEAR_REL_JMP  : 1;
    UINT32    FAR_BRANCH    : 1;
    UINT32    EN_CALL_STACK : 1;
    UINT32    Reserved1     : 22;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_LBR_SELECT_REGISTER;
 
#define MSR_HASWELL_PKGC_IRTL1  0x0000060B
 
typedef union {
  struct {
    UINT32    InterruptResponseTimeLimit : 10;
    UINT32    TimeUnit                   : 3;
    UINT32    Reserved1                  : 2;
    UINT32    Valid                      : 1;
    UINT32    Reserved2                  : 16;
    UINT32    Reserved3                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_PKGC_IRTL1_REGISTER;
 
#define MSR_HASWELL_PKGC_IRTL2  0x0000060C
 
typedef union {
  struct {
    UINT32    InterruptResponseTimeLimit : 10;
    UINT32    TimeUnit                   : 3;
    UINT32    Reserved1                  : 2;
    UINT32    Valid                      : 1;
    UINT32    Reserved2                  : 16;
    UINT32    Reserved3                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_PKGC_IRTL2_REGISTER;
 
#define MSR_HASWELL_PKG_PERF_STATUS  0x00000613
 
#define MSR_HASWELL_DRAM_ENERGY_STATUS  0x00000619
 
#define MSR_HASWELL_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_HASWELL_CONFIG_TDP_NOMINAL  0x00000648
 
typedef union {
  struct {
    UINT32    Config_TDP_Base : 8;
    UINT32    Reserved1       : 24;
    UINT32    Reserved2       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;
 
#define MSR_HASWELL_CONFIG_TDP_LEVEL1  0x00000649
 
typedef union {
  struct {
    UINT32    PKG_TDP_LVL1          : 15;
    UINT32    Reserved1             : 1;
    UINT32    Config_TDP_LVL1_Ratio : 8;
    UINT32    Reserved2             : 8;
    UINT32    PKG_MAX_PWR_LVL1      : 15;
    UINT32    PKG_MIN_PWR_LVL1      : 16;
    UINT32    Reserved3             : 1;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;
 
#define MSR_HASWELL_CONFIG_TDP_LEVEL2  0x0000064A
 
typedef union {
  struct {
    UINT32    PKG_TDP_LVL2          : 15;
    UINT32    Reserved1             : 1;
    UINT32    Config_TDP_LVL2_Ratio : 8;
    UINT32    Reserved2             : 8;
    UINT32    PKG_MAX_PWR_LVL2      : 15;
    UINT32    PKG_MIN_PWR_LVL2      : 16;
    UINT32    Reserved3             : 1;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;
 
#define MSR_HASWELL_CONFIG_TDP_CONTROL  0x0000064B
 
typedef union {
  struct {
    UINT32    TDP_LEVEL       : 2;
    UINT32    Reserved1       : 29;
    UINT32    Config_TDP_Lock : 1;
    UINT32    Reserved2       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;
 
#define MSR_HASWELL_TURBO_ACTIVATION_RATIO  0x0000064C
 
typedef union {
  struct {
    UINT32    MAX_NON_TURBO_RATIO         : 8;
    UINT32    Reserved1                   : 23;
    UINT32    TURBO_ACTIVATION_RATIO_Lock : 1;
    UINT32    Reserved2                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;
 
#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit          : 4;
    UINT32    Reserved1      : 6;
    UINT32    IO_MWAIT       : 1;
    UINT32    Reserved2      : 4;
    UINT32    CFGLock        : 1;
    UINT32    Reserved3      : 9;
    UINT32    C3AutoDemotion : 1;
    UINT32    C1AutoDemotion : 1;
    UINT32    C3Undemotion   : 1;
    UINT32    C1Undemotion   : 1;
    UINT32    Reserved4      : 3;
    UINT32    Reserved5      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_HASWELL_SMM_MCA_CAP  0x0000017D
 
typedef union {
  struct {
    UINT32    Reserved1            : 32;
    UINT32    Reserved2            : 26;
    UINT32    SMM_Code_Access_Chk  : 1;
    UINT32    Long_Flow_Indication : 1;
    UINT32    Reserved3            : 4;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_SMM_MCA_CAP_REGISTER;
 
#define MSR_HASWELL_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Maximum1C : 8;
    UINT32    Maximum2C : 8;
    UINT32    Maximum3C : 8;
    UINT32    Maximum4C : 8;
    UINT32    Reserved  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL  0x00000391
 
typedef union {
  struct {
    UINT32    PMI_Sel_Core0 : 1;
    UINT32    PMI_Sel_Core1 : 1;
    UINT32    PMI_Sel_Core2 : 1;
    UINT32    PMI_Sel_Core3 : 1;
    UINT32    Reserved1     : 15;
    UINT32    Reserved2     : 10;
    UINT32    EN            : 1;
    UINT32    WakePMI       : 1;
    UINT32    FREEZE        : 1;
    UINT32    Reserved3     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;
 
#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS  0x00000392
 
typedef union {
  struct {
    UINT32    Fixed     : 1;
    UINT32    ARB       : 1;
    UINT32    Reserved1 : 1;
    UINT32    CBox      : 1;
    UINT32    Reserved2 : 28;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;
 
#define MSR_HASWELL_UNC_PERF_FIXED_CTRL  0x00000394
 
typedef union {
  struct {
    UINT32    Reserved1      : 20;
    UINT32    EnableOverflow : 1;
    UINT32    Reserved2      : 1;
    UINT32    EnableCounting : 1;
    UINT32    Reserved3      : 9;
    UINT32    Reserved4      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;
 
#define MSR_HASWELL_UNC_PERF_FIXED_CTR  0x00000395
 
typedef union {
  struct {
    UINT32    CurrentCount   : 32;
    UINT32    CurrentCountHi : 16;
    UINT32    Reserved       : 16;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;
 
#define MSR_HASWELL_UNC_CBO_CONFIG  0x00000396
 
typedef union {
  struct {
    UINT32    CBox      : 4;
    UINT32    Reserved1 : 28;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;
 
#define MSR_HASWELL_UNC_ARB_PERFCTR0  0x000003B0
 
#define MSR_HASWELL_UNC_ARB_PERFCTR1  0x000003B1
 
#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0  0x000003B2
 
#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1  0x000003B3
 
#define MSR_HASWELL_SMM_FEATURE_CONTROL  0x000004E0
 
typedef union {
  struct {
    UINT32    Lock      : 1;
    UINT32    Reserved1 : 1;
    UINT32    SMM_Code_Chk_En : 1;
    UINT32    Reserved2       : 29;
    UINT32    Reserved3       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;
 
#define MSR_HASWELL_SMM_DELAYED  0x000004E2
 
#define MSR_HASWELL_SMM_BLOCKED  0x000004E3
 
#define MSR_HASWELL_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnits         : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_HASWELL_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_HASWELL_PP1_POWER_LIMIT  0x00000640
 
#define MSR_HASWELL_PP1_ENERGY_STATUS  0x00000641
 
#define MSR_HASWELL_PP1_POLICY  0x00000642
 
#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS  0x00000690
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                                   : 1;
    UINT32    ThermalStatus                                    : 1;
    UINT32    Reserved1                                        : 2;
    UINT32    GraphicsDriverStatus                             : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlStatus : 1;
    UINT32    VRThermAlertStatus                               : 1;
    UINT32    Reserved2                                        : 1;
    UINT32    ElectricalDesignPointStatus                      : 1;
    UINT32    PLStatus                                         : 1;
    UINT32    PL1Status                                        : 1;
    UINT32    PL2Status                                        : 1;
    UINT32    MaxTurboLimitStatus                              : 1;
    UINT32    TurboTransitionAttenuationStatus                 : 1;
    UINT32    Reserved3                                        : 2;
    UINT32    PROCHOT_Log                                      : 1;
    UINT32    ThermalLog                                       : 1;
    UINT32    Reserved4                                        : 2;
    UINT32    GraphicsDriverLog                                : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlLog    : 1;
    UINT32    VRThermAlertLog                                  : 1;
    UINT32    Reserved5                                        : 1;
    UINT32    ElectricalDesignPointLog                         : 1;
    UINT32    PLLog                                            : 1;
    UINT32    PL1Log                                           : 1;
    UINT32    PL2Log                                           : 1;
    UINT32    MaxTurboLimitLog                                 : 1;
    UINT32    TurboTransitionAttenuationLog                    : 1;
    UINT32    Reserved6                                        : 2;
    UINT32    Reserved7                                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                                   : 1;
    UINT32    ThermalStatus                                    : 1;
    UINT32    Reserved1                                        : 2;
    UINT32    GraphicsDriverStatus                             : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlStatus : 1;
    UINT32    VRThermAlertStatus                               : 1;
    UINT32    Reserved2                                        : 1;
    UINT32    ElectricalDesignPointStatus                      : 1;
    UINT32    GraphicsPowerLimitingStatus                      : 1;
    UINT32    PL1STatus                                        : 1;
    UINT32    PL2Status                                        : 1;
    UINT32    Reserved3                                        : 4;
    UINT32    PROCHOT_Log                                      : 1;
    UINT32    ThermalLog                                       : 1;
    UINT32    Reserved4                                        : 2;
    UINT32    GraphicsDriverLog                                : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlLog    : 1;
    UINT32    VRThermAlertLog                                  : 1;
    UINT32    Reserved5                                        : 1;
    UINT32    ElectricalDesignPointLog                         : 1;
    UINT32    CorePowerLimitingLog                             : 1;
    UINT32    PL1Log                                           : 1;
    UINT32    PL2Log                                           : 1;
    UINT32    MaxTurboLimitLog                                 : 1;
    UINT32    TurboTransitionAttenuationLog                    : 1;
    UINT32    Reserved6                                        : 2;
    UINT32    Reserved7                                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_HASWELL_RING_PERF_LIMIT_REASONS  0x000006B1
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                                : 1;
    UINT32    ThermalStatus                                 : 1;
    UINT32    Reserved1                                     : 4;
    UINT32    VRThermAlertStatus                            : 1;
    UINT32    Reserved2                                     : 1;
    UINT32    ElectricalDesignPointStatus                   : 1;
    UINT32    Reserved3                                     : 1;
    UINT32    PL1STatus                                     : 1;
    UINT32    PL2Status                                     : 1;
    UINT32    Reserved4                                     : 4;
    UINT32    PROCHOT_Log                                   : 1;
    UINT32    ThermalLog                                    : 1;
    UINT32    Reserved5                                     : 2;
    UINT32    GraphicsDriverLog                             : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlLog : 1;
    UINT32    VRThermAlertLog                               : 1;
    UINT32    Reserved6                                     : 1;
    UINT32    ElectricalDesignPointLog                      : 1;
    UINT32    CorePowerLimitingLog                          : 1;
    UINT32    PL1Log                                        : 1;
    UINT32    PL2Log                                        : 1;
    UINT32    MaxTurboLimitLog                              : 1;
    UINT32    TurboTransitionAttenuationLog                 : 1;
    UINT32    Reserved7                                     : 2;
    UINT32    Reserved8                                     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0  0x00000700
 
#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1  0x00000701
 
#define MSR_HASWELL_UNC_CBO_0_PERFCTR0  0x00000706
 
#define MSR_HASWELL_UNC_CBO_0_PERFCTR1  0x00000707
 
#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0  0x00000710
 
#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1  0x00000711
 
#define MSR_HASWELL_UNC_CBO_1_PERFCTR0  0x00000716
 
#define MSR_HASWELL_UNC_CBO_1_PERFCTR1  0x00000717
 
#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0  0x00000720
 
#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1  0x00000721
 
#define MSR_HASWELL_UNC_CBO_2_PERFCTR0  0x00000726
 
#define MSR_HASWELL_UNC_CBO_2_PERFCTR1  0x00000727
 
#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0  0x00000730
 
#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1  0x00000731
 
#define MSR_HASWELL_UNC_CBO_3_PERFCTR0  0x00000736
 
#define MSR_HASWELL_UNC_CBO_3_PERFCTR1  0x00000737
 
#define MSR_HASWELL_PKG_C8_RESIDENCY  0x00000630
 
typedef union {
  struct {
    UINT32    C8ResidencyCounter   : 32;
    UINT32    C8ResidencyCounterHi : 28;
    UINT32    Reserved             : 4;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;
 
#define MSR_HASWELL_PKG_C9_RESIDENCY  0x00000631
 
typedef union {
  struct {
    UINT32    C9ResidencyCounter   : 32;
    UINT32    C9ResidencyCounterHi : 28;
    UINT32    Reserved             : 4;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;
 
#define MSR_HASWELL_PKG_C10_RESIDENCY  0x00000632
 
typedef union {
  struct {
    UINT32    C10ResidencyCounter   : 32;
    UINT32    C10ResidencyCounterHi : 28;
    UINT32    Reserved              : 4;
  } Bits;
  UINT64    Uint64;
} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;
 
#endif