Data Structures
struct	EFI_ATA_DMA_PRD

struct	EFI_ATA_TRANSFER_MODE

struct	EFI_ATA_DRIVE_PARMS

struct	EFI_IDE_REGISTERS

Macros
#define	BMIC_NREAD BIT3

#define	BMIC_START BIT0

#define	BMIS_INTERRUPT BIT2

#define	BMIS_ERROR BIT1

#define	BMIC_OFFSET 0x00

#define	BMIS_OFFSET 0x02

#define	BMID_OFFSET 0x04

#define	EFI_ATA_MODE_DEFAULT_PIO 0x00

#define	EFI_ATA_MODE_FLOW_PIO 0x01

#define	EFI_ATA_MODE_MDMA 0x04

#define	EFI_ATA_MODE_UDMA 0x08

#define	IDE_PRIMARY_OPERATING_MODE BIT0

#define	IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1

#define	IDE_SECONDARY_OPERATING_MODE BIT2

#define	IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3

Enumerations
enum	EFI_IDE_CHANNEL { EfiIdePrimary = 0 , EfiIdeSecondary = 1 , EfiIdeMaxChannel = 2 , IdePrimary = 0 , IdeSecondary = 1 , IdeMaxChannel = 2 }

enum	EFI_IDE_DEVICE { EfiIdeMaster = 0 , EfiIdeSlave = 1 , EfiIdeMaxDevice = 2 , IdeMaster = 0 , IdeSlave = 1 , IdeMaxDevice = 2 }

enum	EFI_ATA_PIO_MODE { EfiAtaPioModeBelow2 , EfiAtaPioMode2 , EfiAtaPioMode3 , EfiAtaPioMode4 }

enum	EFI_ATA_MDMA_MODE { EfiAtaMdmaMode0 , EfiAtaMdmaMode1 , EfiAtaMdmaMode2 }

enum	EFI_ATA_UDMA_MODE { EfiAtaUdmaMode0 , EfiAtaUdmaMode1 , EfiAtaUdmaMode2 , EfiAtaUdmaMode3 , EfiAtaUdmaMode4 , EfiAtaUdmaMode5 }

Functions
EFI_STATUS EFIAPI	GetIdeRegisterIoAddr (IN EFI_PCI_IO_PROTOCOL PciIo, IN OUT EFI_IDE_REGISTERS IdeRegisters)

EFI_STATUS EFIAPI	AtaPacketCommandExecute (IN EFI_PCI_IO_PROTOCOL PciIo, IN EFI_IDE_REGISTERS IdeRegisters, IN UINT8 Channel, IN UINT8 Device, IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet)

Detailed Description

Header file for IDE mode of ATA host controller.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file IdeMode.h.

Macro Definition Documentation

◆ BMIC_NREAD

#define BMIC_NREAD BIT3

Definition at line 58 of file IdeMode.h.

◆ BMIC_OFFSET

#define BMIC_OFFSET 0x00

Definition at line 63 of file IdeMode.h.

◆ BMIC_START

#define BMIC_START BIT0

Definition at line 59 of file IdeMode.h.

◆ BMID_OFFSET

#define BMID_OFFSET 0x04

Definition at line 65 of file IdeMode.h.

◆ BMIS_ERROR

#define BMIS_ERROR BIT1

Definition at line 61 of file IdeMode.h.

◆ BMIS_INTERRUPT

#define BMIS_INTERRUPT BIT2

Definition at line 60 of file IdeMode.h.

◆ BMIS_OFFSET

#define BMIS_OFFSET 0x02

Definition at line 64 of file IdeMode.h.

◆ EFI_ATA_MODE_DEFAULT_PIO

#define EFI_ATA_MODE_DEFAULT_PIO 0x00

Definition at line 70 of file IdeMode.h.

◆ EFI_ATA_MODE_FLOW_PIO

#define EFI_ATA_MODE_FLOW_PIO 0x01

Definition at line 71 of file IdeMode.h.

◆ EFI_ATA_MODE_MDMA

#define EFI_ATA_MODE_MDMA 0x04

Definition at line 72 of file IdeMode.h.

◆ EFI_ATA_MODE_UDMA

#define EFI_ATA_MODE_UDMA 0x08

Definition at line 73 of file IdeMode.h.

◆ IDE_PRIMARY_OPERATING_MODE

#define IDE_PRIMARY_OPERATING_MODE BIT0

Definition at line 113 of file IdeMode.h.

◆ IDE_PRIMARY_PROGRAMMABLE_INDICATOR

#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1

Definition at line 114 of file IdeMode.h.

◆ IDE_SECONDARY_OPERATING_MODE

#define IDE_SECONDARY_OPERATING_MODE BIT2

Definition at line 115 of file IdeMode.h.

◆ IDE_SECONDARY_PROGRAMMABLE_INDICATOR

#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3

Definition at line 116 of file IdeMode.h.

Enumeration Type Documentation

◆ EFI_ATA_MDMA_MODE

enum EFI_ATA_MDMA_MODE

Definition at line 37 of file IdeMode.h.

◆ EFI_ATA_PIO_MODE

enum EFI_ATA_PIO_MODE

PIO mode definition

Definition at line 27 of file IdeMode.h.

◆ EFI_ATA_UDMA_MODE

enum EFI_ATA_UDMA_MODE

Definition at line 46 of file IdeMode.h.

◆ EFI_IDE_CHANNEL

enum EFI_IDE_CHANNEL

Definition at line 12 of file IdeMode.h.

◆ EFI_IDE_DEVICE

enum EFI_IDE_DEVICE

Definition at line 18 of file IdeMode.h.

Function Documentation

◆ AtaPacketCommandExecute()

EFI_STATUS EFIAPI AtaPacketCommandExecute	(	IN EFI_PCI_IO_PROTOCOL *	PciIo,
		IN EFI_IDE_REGISTERS *	IdeRegisters,
		IN UINT8	Channel,
		IN UINT8	Device,
		IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *	Packet
	)

This function is used to send out ATAPI commands conforms to the Packet Command with PIO Data In Protocol.

Parameters

[in]	PciIo	Pointer to the EFI_PCI_IO_PROTOCOL instance
[in]	IdeRegisters	Pointer to EFI_IDE_REGISTERS which is used to store the IDE i/o port registers' base addresses
[in]	Channel	The channel number of device.
[in]	Device	The device number of device.
[in]	Packet	A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.

Return values

EFI_SUCCESS	send out the ATAPI packet command successfully and device sends data successfully.
EFI_DEVICE_ERROR	the device failed to send data.

Definition at line 1806 of file IdeMode.c.

◆ GetIdeRegisterIoAddr()

EFI_STATUS EFIAPI GetIdeRegisterIoAddr	(	IN EFI_PCI_IO_PROTOCOL *	PciIo,
		IN OUT EFI_IDE_REGISTERS *	IdeRegisters
	)

Get IDE i/o port registers' base addresses by mode.

In 'Compatibility' mode, use fixed addresses. In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's Configuration Space.

The steps to get IDE i/o port registers' base addresses for each channel as follows:

Examine the Programming Interface byte of the Class Code fields in PCI IDE controller's Configuration Space to determine the operating mode.
a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
| | Command Block | Control Block | | Channel | Registers | Registers | |___________|_______________|_______________| | Primary | 1F0h - 1F7h | 3F6h - 3F7h | |___________|_______________|_______________| | Secondary | 170h - 177h | 376h - 377h | |___________|_______________|_______________|

Table 1. Compatibility resource mappings

b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs in IDE controller's PCI Configuration Space, shown in the Table 2 below.

| | Command Block | Control Block | | Channel | Registers | Registers | |___________|___________________|___________________| | Primary | BAR at offset 0x10| BAR at offset 0x14| |___________|___________________|___________________| | Secondary | BAR at offset 0x18| BAR at offset 0x1C| |___________|___________________|___________________|

Table 2. BARs for Register Mapping