IoApicLib.c File Reference

#include <Base.h>
#include <Library/IoApicLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/LocalApicLib.h>
#include <Register/IoApic.h>

Go to the source code of this file.

Functions
UINT32 EFIAPI	IoApicRead (IN UINTN Index)
UINT32 EFIAPI	IoApicWrite (IN UINTN Index, IN UINT32 Value)
VOID EFIAPI	IoApicEnableInterrupt (IN UINTN Irq, IN BOOLEAN Enable)
VOID EFIAPI	IoApicConfigureInterrupt (IN UINTN Irq, IN UINTN Vector, IN UINTN DeliveryMode, IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel)

Detailed Description

I/O APIC library.

I/O APIC library assumes I/O APIC is enabled. It does not handles cases where I/O APIC is disabled.

Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file IoApicLib.c.

Function Documentation

IoApicConfigureInterrupt()

VOID EFIAPI IoApicConfigureInterrupt	(	IN UINTN	Irq,
		IN UINTN	Vector,
		IN UINTN	DeliveryMode,
		IN BOOLEAN	LevelTriggered,
		IN BOOLEAN	AssertionLevel
	)

Configures an I/O APIC interrupt.

Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical mode to the Local APIC of the currently executing CPU. The default state of the entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must be used to enable(unmask) the I/O APIC Interrupt.

If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). If Vector >= 0x100, then ASSERT(). If DeliveryMode is not supported, then ASSERT().

Parameters

Irq	Specifies the I/O APIC interrupt to initialize.
Vector	The 8-bit interrupt vector associated with the I/O APIC Interrupt. Must be in the range 0x10..0xFE.
DeliveryMode	A 3-bit value that specifies how the recept of the I/O APIC interrupt is handled. The only supported values are: 0: IO_APIC_DELIVERY_MODE_FIXED 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 2: IO_APIC_DELIVERY_MODE_SMI 4: IO_APIC_DELIVERY_MODE_NMI 5: IO_APIC_DELIVERY_MODE_INIT 7: IO_APIC_DELIVERY_MODE_EXTINT
LevelTriggered	TRUE specifies a level triggered interrupt. FALSE specifies an edge triggered interrupt.
AssertionLevel	TRUE specified an active high interrupt. FALSE specifies an active low interrupt.

Definition at line 123 of file IoApicLib.c.

IoApicEnableInterrupt()

VOID EFIAPI IoApicEnableInterrupt	(	IN UINTN	Irq,
		IN BOOLEAN	Enable
	)

Set the interrupt mask of an I/O APIC interrupt.

If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().

Parameters

Irq	Specifies the I/O APIC interrupt to enable or disable.
Enable	If TRUE, then enable the I/O APIC interrupt specified by Irq. If FALSE, then disable the I/O APIC interrupt specified by Irq.

Definition at line 76 of file IoApicLib.c.

IoApicRead()

UINT32 EFIAPI IoApicRead

(

IN UINTN

Index

)

Read a 32-bit I/O APIC register.

If Index is >= 0x100, then ASSERT().

Parameters

Index

Specifies the I/O APIC register to read.

Returns

The 32-bit value read from the I/O APIC register specified by Index.

Definition at line 34 of file IoApicLib.c.

IoApicWrite()

UINT32 EFIAPI IoApicWrite	(	IN UINTN	Index,
		IN UINT32	Value
	)

Write a 32-bit I/O APIC register.

If Index is >= 0x100, then ASSERT().

Parameters

Index	Specifies the I/O APIC register to write.
Value	Specifies the value to write to the I/O APIC register specified by Index.

Returns

The 32-bit value written to I/O APIC register specified by Index.

Definition at line 55 of file IoApicLib.c.