LoongArchCache.c File Reference

#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>

Go to the source code of this file.

Functions
VOID EFIAPI	AsmDataBarrierLoongArch (VOID)
VOID EFIAPI	AsmInstructionBarrierLoongArch (VOID)
VOID EFIAPI	InvalidateInstructionCache (VOID)
VOID *EFIAPI	InvalidateInstructionCacheRange (IN VOID *Address, IN UINTN Length)
VOID EFIAPI	WriteBackInvalidateDataCache (VOID)
VOID *EFIAPI	WriteBackInvalidateDataCacheRange (IN VOID *Address, IN UINTN Length)
VOID EFIAPI	WriteBackDataCache (VOID)
VOID *EFIAPI	WriteBackDataCacheRange (IN VOID *Address, IN UINTN Length)
VOID EFIAPI	InvalidateDataCache (VOID)
VOID *EFIAPI	InvalidateDataCacheRange (IN VOID *Address, IN UINTN Length)

Detailed Description

Cache Maintenance Functions for LoongArch. LoongArch cache maintenance functions has not yet been completed, and will added in later. Functions are null functions now.

Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file LoongArchCache.c.

Function Documentation

AsmDataBarrierLoongArch()

VOID EFIAPI AsmDataBarrierLoongArch

(

VOID

)

LoongArch data barrier operation.

AsmInstructionBarrierLoongArch()

VOID EFIAPI AsmInstructionBarrierLoongArch

(

VOID

)

LoongArch instruction barrier operation.

InvalidateDataCache()

VOID EFIAPI InvalidateDataCache

(

VOID

)

Invalidates the entire data cache in cache coherency domain of the calling CPU.

Invalidates the entire data cache in cache coherency domain of the calling CPU. This function must be used with care because dirty cache lines are not written back to system memory. It is typically used for cache diagnostics. If the CPU does not support invalidation of the entire data cache, then a write back and invalidate operation should be performed on the entire data cache.

Definition at line 211 of file LoongArchCache.c.

InvalidateDataCacheRange()

VOID *EFIAPI InvalidateDataCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Invalidates a range of data cache lines in the cache coherency domain of the calling CPU.

Invalidates the data cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire data cache line containing Address is invalidated. If Address + Length is not aligned on a cache line boundary, then the entire data cache line containing Address + Length -1 is invalidated. This function must never invalidate any cache lines outside the specified range. If Length is 0, the no data cache lines are invalidated. Address is returned. This function must be used with care because dirty cache lines are not written back to system memory. It is typically used for cache diagnostics. If the CPU does not support invalidation of a data cache range, then a write back and invalidate operation should be performed on the data cache range.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

[in]	Address	The base address of the data cache lines to invalidate. If the CPU is in a physical addressing mode, then Address is a physical address. If the CPU is in a virtual addressing mode, then Address is a virtual address.
[in]	Length	The number of bytes to invalidate from the data cache.

Returns

Address.

Definition at line 247 of file LoongArchCache.c.

InvalidateInstructionCache()

VOID EFIAPI InvalidateInstructionCache

(

VOID

)

Invalidates the entire instruction cache in cache coherency domain of the calling CPU.

Definition at line 44 of file LoongArchCache.c.

InvalidateInstructionCacheRange()

VOID *EFIAPI InvalidateInstructionCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Invalidates a range of instruction cache lines in the cache coherency domain of the calling CPU.

Invalidates the instruction cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire instruction cache line containing Address is invalidated. If Address + Length is not aligned on a cache line boundary, then the entire instruction cache line containing Address + Length -1 is invalidated. This function may choose to invalidate the entire instruction cache if that is more efficient than invalidating the specified range. If Length is 0, the no instruction cache lines are invalidated. Address is returned.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

[in]	Address	The base address of the instruction cache lines to invalidate. If the CPU is in a physical addressing mode, then Address is a physical address. If the CPU is in a virtual addressing mode, then Address is a virtual address.
[in]	Length	The number of bytes to invalidate from the instruction cache.

Returns

Address.

Definition at line 78 of file LoongArchCache.c.

WriteBackDataCache()

VOID EFIAPI WriteBackDataCache

(

VOID

)

Writes Back the entire data cache in cache coherency domain of the calling CPU.

Writes Back the entire data cache in cache coherency domain of the calling CPU. This function guarantees that all dirty cache lines are written back to system memory. This function may also invalidate all the data cache lines in the cache coherency domain of the calling CPU.

Definition at line 155 of file LoongArchCache.c.

WriteBackDataCacheRange()

VOID *EFIAPI WriteBackDataCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Writes Back a range of data cache lines in the cache coherency domain of the calling CPU.

Writes Back the data cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire data cache line containing Address is written back. If Address + Length is not aligned on a cache line boundary, then the entire data cache line containing Address + Length -1 is written back. This function may choose to write back the entire data cache if that is more efficient than writing back the specified range. If Length is 0, the no data cache lines are written back. This function may also invalidate all the data cache lines in the specified range of the cache coherency domain of the calling CPU. Address is returned.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

[in]	Address	The base address of the data cache lines to write back. If the CPU is in a physical addressing mode, then Address is a physical address. If the CPU is in a virtual addressing mode, then Address is a virtual address.
[in]	Length	The number of bytes to write back from the data cache.

Returns

Address of cache written in main memory.

Definition at line 189 of file LoongArchCache.c.

WriteBackInvalidateDataCache()

VOID EFIAPI WriteBackInvalidateDataCache

(

VOID

)

Writes Back and Invalidates the entire data cache in cache coherency domain of the calling CPU.

Writes Back and Invalidates the entire data cache in cache coherency domain of the calling CPU. This function guarantees that all dirty cache lines are written back to system memory, and also invalidates all the data cache lines in the cache coherency domain of the calling CPU.

Definition at line 99 of file LoongArchCache.c.

WriteBackInvalidateDataCacheRange()

VOID *EFIAPI WriteBackInvalidateDataCacheRange	(	IN VOID *	Address,
		IN UINTN	Length
	)

Writes Back and Invalidates a range of data cache lines in the cache coherency domain of the calling CPU.

Writes Back and Invalidate the data cache lines specified by Address and Length. If Address is not aligned on a cache line boundary, then entire data cache line containing Address is written back and invalidated. If Address + Length is not aligned on a cache line boundary, then the entire data cache line containing Address + Length -1 is written back and invalidated. This function may choose to write back and invalidate the entire data cache if that is more efficient than writing back and invalidating the specified range. If Length is 0, the no data cache lines are written back and invalidated. Address is returned.

If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

Parameters

[in]	Address	The base address of the data cache lines to write back and invalidate. If the CPU is in a physical addressing mode, then Address is a physical address. If the CPU is in a virtual addressing mode, then Address is a virtual address.
[in]	Length	The number of bytes to write back and invalidate from the data cache.

Returns

Address of cache invalidation.

Definition at line 134 of file LoongArchCache.c.