TianoCore EDK2 master
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MpEqu.inc
1;------------------------------------------------------------------------------ ;
2; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
3; SPDX-License-Identifier: BSD-2-Clause-Patent
4;
5; Module Name:
6;
7; MpEqu.inc
8;
9; Abstract:
10;
11; This is the equates file for Multiple Processor support
12;
13;-------------------------------------------------------------------------------
14%include "Nasm.inc"
15
16CPU_SWITCH_STATE_IDLE equ 0
17CPU_SWITCH_STATE_STORED equ 1
18CPU_SWITCH_STATE_LOADED equ 2
19
20;
21; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP
22;
23struc MP_ASSEMBLY_ADDRESS_MAP
24 .RendezvousFunnelAddress CTYPE_UINTN 1
25 .ModeEntryOffset CTYPE_UINTN 1
26 .RendezvousFunnelSize CTYPE_UINTN 1
27 .RelocateApLoopFuncAddressGeneric CTYPE_UINTN 1
28 .RelocateApLoopFuncSizeGeneric CTYPE_UINTN 1
29 .RelocateApLoopFuncAddressAmdSev CTYPE_UINTN 1
30 .RelocateApLoopFuncSizeAmdSev CTYPE_UINTN 1
31 .ModeTransitionOffset CTYPE_UINTN 1
32 .SwitchToRealNoNxOffset CTYPE_UINTN 1
33 .SwitchToRealPM16ModeOffset CTYPE_UINTN 1
34 .SwitchToRealPM16ModeSize CTYPE_UINTN 1
35endstruc
36
37;
38; Equivalent NASM structure of IA32_DESCRIPTOR
39;
40struc IA32_DESCRIPTOR
41 .Limit CTYPE_UINT16 1
42 .Base CTYPE_UINTN 1
43endstruc
44
45;
46; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO
47;
48struc CPU_EXCHANGE_ROLE_INFO
49 ; State is defined as UINT8 in C header file
50 ; Define it as UINTN here to guarantee the fields that follow State
51 ; is naturally aligned. The structure layout doesn't change.
52 .State CTYPE_UINTN 1
53 .StackPointer CTYPE_UINTN 1
54 .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size
55 .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size
56endstruc
57
58;
59; Equivalent NASM structure of CPU_INFO_IN_HOB
60;
61struc CPU_INFO_IN_HOB
62 .InitialApicId CTYPE_UINT32 1
63 .ApicId CTYPE_UINT32 1
64 .Health CTYPE_UINT32 1
65 .ApTopOfStack CTYPE_UINT64 1
66endstruc
67
68;
69; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO
70; Assembly routines should refrain from directly interacting with
71; the internal details of CPU_MP_DATA.
72;
73struc MP_CPU_EXCHANGE_INFO
74 .StackStart: CTYPE_UINTN 1
75 .StackSize: CTYPE_UINTN 1
76 .CFunction: CTYPE_UINTN 1
77 .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size
78 .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size
79 .BufferStart: CTYPE_UINTN 1
80 .ModeOffset: CTYPE_UINTN 1
81 .ApIndex: CTYPE_UINTN 1
82 .CodeSegment: CTYPE_UINTN 1
83 .DataSegment: CTYPE_UINTN 1
84 .EnableExecuteDisable: CTYPE_UINTN 1
85 .Cr3: CTYPE_UINTN 1
86 .InitFlag: CTYPE_UINTN 1
87 .CpuInfo: CTYPE_UINTN 1
88 .NumApsExecuting: CTYPE_UINTN 1
89 .CpuMpData: CTYPE_UINTN 1
90 .InitializeFloatingPointUnits: CTYPE_UINTN 1
91 .ModeTransitionMemory: CTYPE_UINT32 1
92 .ModeTransitionSegment: CTYPE_UINT16 1
93 .ModeHighMemory: CTYPE_UINT32 1
94 .ModeHighSegment: CTYPE_UINT16 1
95 .Enable5LevelPaging: CTYPE_BOOLEAN 1
96 .SevEsIsEnabled: CTYPE_BOOLEAN 1
97 .SevSnpIsEnabled CTYPE_BOOLEAN 1
98 .GhcbBase: CTYPE_UINTN 1
99 .ExtTopoAvail: CTYPE_BOOLEAN 1
100endstruc
101
102MP_CPU_EXCHANGE_INFO_OFFSET equ (Flat32Start - RendezvousFunnelProcStart)
103%define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO. %+ Field)
UINTN
UINT64 UINTN
Definition: ProcessorBind.h:112
CPU_EXCHANGE_ROLE_INFO
Definition: MpLib.h:104
MP_ASSEMBLY_ADDRESS_MAP
Definition: MpLib.h:187