MpLib.h

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#ifndef _MP_LIB_H_
#define _MP_LIB_H_
 
#include <PiPei.h>
 
#include <Register/Intel/Cpuid.h>
#include <Register/Amd/Cpuid.h>
#include <Register/Amd/Ghcb.h>
#include <Register/Intel/Msr.h>
#include <Register/Intel/LocalApic.h>
#include <Register/Intel/Microcode.h>
 
#include <Library/MpInitLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/LocalApicLib.h>
#include <Library/CpuLib.h>
#include <Library/TimerLib.h>
#include <Library/SynchronizationLib.h>
#include <Library/MtrrLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/MicrocodeLib.h>
#include <Library/CpuPageTableLib.h>
#include <Library/SafeIntLib.h>
#include <ConfidentialComputingGuestAttr.h>
 
#include <Register/Amd/SevSnpMsr.h>
#include <Register/Amd/Ghcb.h>
 
#include <Guid/MicrocodePatchHob.h>
#include "MpHandOff.h"
 
#define WAKEUP_AP_SIGNAL  SIGNATURE_32 ('S', 'T', 'A', 'P')
//
// To trigger the start-up signal, BSP writes the specified
// StartupSignalValue to the StartupSignalAddress of each processor.
// This address is monitored by the APs, and as soon as they receive
// the value that matches the MP_HAND_OFF_SIGNAL, they will wake up
// and switch the context from PEI to DXE phase.
//
#define MP_HAND_OFF_SIGNAL  SIGNATURE_32 ('M', 'P', 'H', 'O')
 
#define CPU_INIT_MP_LIB_HOB_GUID \
  { \
    0x58eb6a19, 0x3699, 0x4c68, { 0xa8, 0x36, 0xda, 0xcd, 0x8e, 0xdc, 0xad, 0x4a } \
  }
 
//
//  The MP data for switch BSP
//
#define CPU_SWITCH_STATE_IDLE    0
#define CPU_SWITCH_STATE_STORED  1
#define CPU_SWITCH_STATE_LOADED  2
 
//
// Default maximum number of entries to store the microcode patches information
//
#define DEFAULT_MAX_MICROCODE_PATCH_NUM  8
 
#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull
 
//
// Data structure for microcode patch information
//
typedef struct {
  UINTN    Address;
  UINTN    Size;
} MICROCODE_PATCH_INFO;
 
//
// CPU volatile registers around INIT-SIPI-SIPI
//
typedef struct {
  UINTN              Cr0;
  UINTN              Cr3;
  UINTN              Cr4;
  UINTN              Dr0;
  UINTN              Dr1;
  UINTN              Dr2;
  UINTN              Dr3;
  UINTN              Dr6;
  UINTN              Dr7;
  IA32_DESCRIPTOR    Gdtr;
  IA32_DESCRIPTOR    Idtr;
  UINT16             Tr;
} CPU_VOLATILE_REGISTERS;
 
//
// CPU exchange information for switch BSP
//
typedef struct {
  UINT8                     State;             // offset 0
  UINTN                     StackPointer;      // offset 4 / 8
  CPU_VOLATILE_REGISTERS    VolatileRegisters; // offset 8 / 16
} CPU_EXCHANGE_ROLE_INFO;
 
//
// AP loop state when APs are in idle state
// It's value is the same with PcdCpuApLoopMode
//
typedef enum {
  ApInHltLoop   = 1,
  ApInMwaitLoop = 2,
  ApInRunLoop   = 3
} AP_LOOP_MODE;
 
//
// AP initialization state during APs wakeup
//
typedef enum {
  ApInitConfig = 1,
  ApInitDone   = 2
} AP_INIT_STATE;
 
//
// AP state
//
// The state transitions for an AP when it process a procedure are:
//  Idle ----> Ready ----> Busy ----> Idle
//       [BSP]       [AP]       [AP]
//
typedef enum {
  CpuStateIdle,
  CpuStateReady,
  CpuStateBusy,
  CpuStateFinished,
  CpuStateDisabled
} CPU_STATE;
 
//
// AP related data
//
typedef struct {
  SPIN_LOCK                 ApLock;
  volatile UINT32           *StartupApSignal;
  volatile UINTN            ApFunction;
  volatile UINTN            ApFunctionArgument;
  BOOLEAN                   CpuHealthy;
  volatile CPU_STATE        State;
  CPU_VOLATILE_REGISTERS    VolatileRegisters;
  BOOLEAN                   Waiting;
  BOOLEAN                   *Finished;
  UINT64                    ExpectedTime;
  UINT64                    CurrentTime;
  UINT64                    TotalTime;
  EFI_EVENT                 WaitEvent;
  UINT32                    ProcessorSignature;
  UINT8                     PlatformId;
  UINT64                    MicrocodeEntryAddr;
  UINT32                    MicrocodeRevision;
  SEV_ES_SAVE_AREA          *SevEsSaveArea;
} CPU_AP_DATA;
 
//
// Basic CPU information saved in Guided HOB.
// Because the contents will be shard between PEI and DXE,
// we need to make sure the each fields offset same in different
// architecture.
//
#pragma pack (1)
typedef struct {
  UINT32    InitialApicId;
  UINT32    ApicId;
  UINT32    Health;
  UINT64    ApTopOfStack;
} CPU_INFO_IN_HOB;
#pragma pack ()
 
//
// AP reset code information including code address and size,
// this structure will be shared be C code and assembly code.
// It is natural aligned by design.
//
typedef struct {
  UINT8    *RendezvousFunnelAddress;
  UINTN    ModeEntryOffset;
  UINTN    RendezvousFunnelSize;
  UINT8    *RelocateApLoopFuncAddressGeneric;
  UINTN    RelocateApLoopFuncSizeGeneric;
  UINT8    *RelocateApLoopFuncAddressAmdSev;
  UINTN    RelocateApLoopFuncSizeAmdSev;
  UINTN    ModeTransitionOffset;
  UINTN    SwitchToRealNoNxOffset;
  UINTN    SwitchToRealPM16ModeOffset;
  UINTN    SwitchToRealPM16ModeSize;
} MP_ASSEMBLY_ADDRESS_MAP;
 
typedef struct _CPU_MP_DATA CPU_MP_DATA;
 
#pragma pack(1)
 
//
// MP CPU exchange information for AP reset code
// This structure is required to be packed because fixed field offsets
// into this structure are used in assembly code in this module
// Assembly routines should refrain from directly interacting with
// the internal details of CPU_MP_DATA.
//
typedef struct {
  UINTN              StackStart;
  UINTN              StackSize;
  UINTN              CFunction;
  IA32_DESCRIPTOR    GdtrProfile;
  IA32_DESCRIPTOR    IdtrProfile;
  UINTN              BufferStart;
  UINTN              ModeOffset;
  UINTN              ApIndex;
  UINTN              CodeSegment;
  UINTN              DataSegment;
  UINTN              EnableExecuteDisable;
  UINTN              Cr3;
  UINTN              InitFlag;
  CPU_INFO_IN_HOB    *CpuInfo;
  UINTN              NumApsExecuting;
  CPU_MP_DATA        *CpuMpData;
  UINTN              InitializeFloatingPointUnitsAddress;
  UINT32             ModeTransitionMemory;
  UINT16             ModeTransitionSegment;
  UINT32             ModeHighMemory;
  UINT16             ModeHighSegment;
  //
  // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.
  //
  BOOLEAN            Enable5LevelPaging;
  BOOLEAN            SevEsIsEnabled;
  BOOLEAN            SevSnpIsEnabled;
  UINTN              GhcbBase;
  BOOLEAN            ExtTopoAvail;
} MP_CPU_EXCHANGE_INFO;
 
#pragma pack()
 
//
// CPU MP Data save in memory, and intended for use in C code.
// There are some duplicated fields, such as XD status, between
// CpuMpData and ExchangeInfo. These duplications in CpuMpData
// are present to avoid to be direct accessed and comprehended
// in assembly code.
//
struct _CPU_MP_DATA {
  UINT64       CpuInfoInHob;
  UINT32       CpuCount;
  UINT32       BspNumber;
  SPIN_LOCK    MpLock;
  UINTN        Buffer;
 
  //
  // InitialBspApicMode stores the initial BSP APIC mode.
  // It is used to synchronize the BSP APIC mode with APs
  // in the first time APs wake up.
  // Its value doesn't reflect the current APIC mode since there are
  // two cases the APIC mode is changed:
  // 1. MpLib explicitly switches to X2 APIC mode because number of threads is greater than 255,
  //    or there are any logical processors reporting an initial APIC ID of 255 or greater.
  // 2. Some code switches to X2 APIC mode in all threads through MP services PPI/Protocol.
  //
  UINTN                            InitialBspApicMode;
  UINTN                            CpuApStackSize;
  MP_ASSEMBLY_ADDRESS_MAP          AddressMap;
  UINTN                            WakeupBuffer;
  UINTN                            WakeupBufferHigh;
  UINTN                            BackupBuffer;
  UINTN                            BackupBufferSize;
 
  volatile UINT32                  FinishedCount;
  UINT32                           RunningCount;
  BOOLEAN                          SingleThread;
  EFI_AP_PROCEDURE                 Procedure;
  VOID                             *ProcArguments;
  BOOLEAN                          *Finished;
  UINT64                           ExpectedTime;
  UINT64                           CurrentTime;
  UINT64                           TotalTime;
  EFI_EVENT                        WaitEvent;
  UINTN                            **FailedCpuList;
  BOOLEAN                          EnableExecuteDisableForSwitchContext;
 
  AP_INIT_STATE                    InitFlag;
  BOOLEAN                          SwitchBspFlag;
  UINTN                            NewBspNumber;
  CPU_EXCHANGE_ROLE_INFO           BSPInfo;
  CPU_EXCHANGE_ROLE_INFO           APInfo;
  MTRR_SETTINGS                    MtrrTable;
  UINT8                            ApLoopMode;
  UINT8                            ApTargetCState;
  UINT16                           PmCodeSegment;
  UINT16                           Pm16CodeSegment;
  CPU_AP_DATA                      *CpuData;
  volatile MP_CPU_EXCHANGE_INFO    *MpCpuExchangeInfo;
 
  UINT32                           InitTimerCount;
  UINTN                            DivideValue;
  UINT8                            Vector;
  BOOLEAN                          PeriodicMode;
  BOOLEAN                          TimerInterruptState;
  UINT64                           MicrocodePatchAddress;
  UINT64                           MicrocodePatchRegionSize;
 
  //
  // Whether need to use Init-Sipi-Sipi to wake up the APs.
  // Two cases need to set this value to TRUE. One is in HLT
  // loop mode, the other is resume from S3 which loop mode
  // will be hardcode change to HLT mode by PiSmmCpuDxeSmm
  // driver.
  //
  BOOLEAN        WakeUpByInitSipiSipi;
 
  BOOLEAN        SevEsIsEnabled;
  BOOLEAN        SevSnpIsEnabled;
  BOOLEAN        UseSevEsAPMethod;
  UINTN          SevEsAPBuffer;
  UINTN          SevEsAPResetStackStart;
  CPU_MP_DATA    *NewCpuMpData;
 
  UINT64         GhcbBase;
};
 
//
// AP_STACK_DATA is stored at the top of each AP stack.
//
typedef struct {
  UINTN          Bist;
  CPU_MP_DATA    *MpData;
} AP_STACK_DATA;
 
#define AP_SAFE_STACK_SIZE   128
#define AP_RESET_STACK_SIZE  AP_SAFE_STACK_SIZE
STATIC_ASSERT ((AP_SAFE_STACK_SIZE & (CPU_STACK_ALIGNMENT - 1)) == 0, "AP_SAFE_STACK_SIZE is not aligned with CPU_STACK_ALIGNMENT");
 
#pragma pack(1)
 
typedef struct {
  UINT8     InsnBuffer[8];
  UINT16    Rip;
  UINT16    Segment;
} SEV_ES_AP_JMP_FAR;
 
#pragma pack()
 
typedef
  VOID
(EFIAPI AP_RESET)(
  IN UINTN    BufferStart,
  IN UINT16   Code16,
  IN UINT16   Code32,
  IN UINTN    StackStart
  );
 
extern EFI_GUID         mCpuInitMpLibHobGuid;
extern volatile UINT32  mNumberToFinish;
 
typedef
  VOID
(EFIAPI *ASM_RELOCATE_AP_LOOP_GENERIC)(
  IN BOOLEAN                 MwaitSupport,
  IN UINTN                   ApTargetCState,
  IN UINTN                   TopOfApStack,
  IN UINTN                   NumberToFinish,
  IN UINTN                   Cr3
  );
 
typedef
  VOID
(EFIAPI *ASM_RELOCATE_AP_LOOP_AMDSEV)(
  IN BOOLEAN                 MwaitSupport,
  IN UINTN                   ApTargetCState,
  IN UINTN                   PmCodeSegment,
  IN UINTN                   TopOfApStack,
  IN UINTN                   NumberToFinish,
  IN UINTN                   Pm16CodeSegment,
  IN UINTN                   SevEsAPJumpTable,
  IN UINTN                   WakeupBuffer
  );
 
VOID
EFIAPI
AsmGetAddressMap (
  OUT MP_ASSEMBLY_ADDRESS_MAP  *AddressMap
  );
 
VOID
EFIAPI
AsmExchangeRole (
  IN CPU_EXCHANGE_ROLE_INFO  *MyInfo,
  IN CPU_EXCHANGE_ROLE_INFO  *OthersInfo
  );
 
typedef union {
  VOID                            *Data;
  ASM_RELOCATE_AP_LOOP_AMDSEV     AmdSevEntry;  // 64-bit AMD Sev processors
  ASM_RELOCATE_AP_LOOP_GENERIC    GenericEntry; // Intel processors (32-bit or 64-bit), 32-bit AMD processors, or AMD non-Sev processors
} RELOCATE_AP_LOOP_ENTRY;
 
CPU_MP_DATA *
GetCpuMpData (
  VOID
  );
 
VOID
SaveCpuMpData (
  IN CPU_MP_DATA  *CpuMpData
  );
 
UINTN
GetWakeupBuffer (
  IN UINTN  WakeupBufferSize
  );
 
VOID
SwitchApContext (
  IN CONST MP_HAND_OFF_CONFIG  *MpHandOffConfig,
  IN CONST MP_HAND_OFF         *FirstMpHandOff
  );
 
MP_HAND_OFF *
GetNextMpHandOffHob (
  IN CONST MP_HAND_OFF  *MpHandOff
  );
 
UINTN
AllocateCodeBuffer (
  IN UINTN  BufferSize
  );
 
UINTN
GetSevEsAPMemory (
  VOID
  );
 
UINTN
CreatePageTable (
  IN UINTN  Address,
  IN UINTN  Length
  );
 
VOID
WakeUpAP (
  IN CPU_MP_DATA       *CpuMpData,
  IN BOOLEAN           Broadcast,
  IN UINTN             ProcessorNumber,
  IN EFI_AP_PROCEDURE  Procedure               OPTIONAL,
  IN VOID              *ProcedureArgument      OPTIONAL,
  IN BOOLEAN           WakeUpDisabledAps
  );
 
VOID
InitMpGlobalData (
  IN CPU_MP_DATA  *CpuMpData
  );
 
EFI_STATUS
StartupAllCPUsWorker (
  IN  EFI_AP_PROCEDURE  Procedure,
  IN  BOOLEAN           SingleThread,
  IN  BOOLEAN           ExcludeBsp,
  IN  EFI_EVENT         WaitEvent               OPTIONAL,
  IN  UINTN             TimeoutInMicroseconds,
  IN  VOID              *ProcedureArgument      OPTIONAL,
  OUT UINTN             **FailedCpuList         OPTIONAL
  );
 
EFI_STATUS
StartupThisAPWorker (
  IN  EFI_AP_PROCEDURE  Procedure,
  IN  UINTN             ProcessorNumber,
  IN  EFI_EVENT         WaitEvent               OPTIONAL,
  IN  UINTN             TimeoutInMicroseconds,
  IN  VOID              *ProcedureArgument      OPTIONAL,
  OUT BOOLEAN           *Finished               OPTIONAL
  );
 
EFI_STATUS
SwitchBSPWorker (
  IN UINTN    ProcessorNumber,
  IN BOOLEAN  EnableOldBSP
  );
 
EFI_STATUS
EnableDisableApWorker (
  IN  UINTN    ProcessorNumber,
  IN  BOOLEAN  EnableAP,
  IN  UINT32   *HealthFlag OPTIONAL
  );
 
CPU_MP_DATA *
GetCpuMpDataFromGuidedHob (
  VOID
  );
 
EFI_STATUS
CheckThisAP (
  IN UINTN  ProcessorNumber
  );
 
EFI_STATUS
CheckAllAPs (
  VOID
  );
 
VOID
CheckAndUpdateApsStatus (
  VOID
  );
 
VOID
MicrocodeDetect (
  IN CPU_MP_DATA  *CpuMpData,
  IN UINTN        ProcessorNumber
  );
 
VOID
ShadowMicrocodeUpdatePatch (
  IN OUT CPU_MP_DATA  *CpuMpData
  );
 
BOOLEAN
GetMicrocodePatchInfoFromHob (
  UINT64  *Address,
  UINT64  *RegionSize
  );
 
BOOLEAN
IsMwaitSupport (
  VOID
  );
 
VOID
EnableDebugAgent (
  VOID
  );
 
EFI_STATUS
GetProcessorNumber (
  IN CPU_MP_DATA  *CpuMpData,
  OUT UINTN       *ProcessorNumber
  );
 
EFI_STATUS
PlatformShadowMicrocode (
  IN OUT CPU_MP_DATA  *CpuMpData
  );
 
VOID
AllocateSevEsAPMemory (
  IN OUT CPU_MP_DATA  *CpuMpData
  );
 
VOID
SetSevEsJumpTable (
  IN UINTN  SipiVector
  );
 
VOID
SevEsPlaceApHlt (
  CPU_MP_DATA  *CpuMpData
  );
 
BOOLEAN
EFIAPI
ConfidentialComputingGuestHas (
  CONFIDENTIAL_COMPUTING_GUEST_ATTR  Attr
  );
 
VOID
FillExchangeInfoDataSevEs (
  IN volatile MP_CPU_EXCHANGE_INFO  *ExchangeInfo
  );
 
VOID
SevSnpCreateSaveArea (
  IN CPU_MP_DATA  *CpuMpData,
  IN CPU_AP_DATA  *CpuData,
  UINT32          ApicId
  );
 
VOID
SevSnpCreateAP (
  IN CPU_MP_DATA  *CpuMpData,
  IN INTN         ProcessorNumber
  );
 
BOOLEAN
CanUseSevSnpCreateAP (
  IN  CPU_MP_DATA  *CpuMpData
  );
 
VOID
AmdSevUpdateCpuMpData (
  IN CPU_MP_DATA  *CpuMpData
  );
 
VOID
PrepareApLoopCode (
  IN CPU_MP_DATA  *CpuMpData
  );
 
VOID
EFIAPI
RelocateApLoop (
  IN OUT VOID  *Buffer
  );
 
VOID
AllocateApLoopCodeBuffer (
  IN UINTN                     Pages,
  IN OUT EFI_PHYSICAL_ADDRESS  *Address
  );
 
VOID
RemoveNxprotection (
  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
  IN UINTN                 Length
  );
 
#endif