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NvmExpressPeiHci.h File Reference

Go to the source code of this file.

Macros

#define NVME_GET_CAP(Private, Cap)   NvmeMmioRead (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))
 
#define NVME_GET_CC(Private, Cc)   NvmeMmioRead (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))
 
#define NVME_SET_CC(Private, Cc)   NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))
 
#define NVME_GET_CSTS(Private, Csts)   NvmeMmioRead (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))
 
#define NVME_GET_AQA(Private, Aqa)   NvmeMmioRead (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))
 
#define NVME_SET_AQA(Private, Aqa)   NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))
 
#define NVME_GET_ASQ(Private, Asq)   NvmeMmioRead (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))
 
#define NVME_SET_ASQ(Private, Asq)   NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))
 
#define NVME_GET_ACQ(Private, Acq)   NvmeMmioRead (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))
 
#define NVME_SET_ACQ(Private, Acq)   NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))
 
#define NVME_GET_VER(Private, Ver)   NvmeMmioRead (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))
 
#define NVME_SET_SQTDBL(Private, Qid, Sqtdbl)   NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))
 
#define NVME_SET_CQHDBL(Private, Qid, Cqhdbl)   NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))
 
#define ALIGN(v, a)   (UINTN)((((v) - 1) | ((a) - 1)) + 1)
 
#define NVME_MEM_BASE(Private)   ((UINTN)(Private->Buffer))
 
#define NVME_ASQ_BASE(Private)   (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
 
#define NVME_ACQ_BASE(Private)   (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
 
#define NVME_SQ_BASE(Private, Index)   (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
 
#define NVME_CQ_BASE(Private, Index)   (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
 
#define NVME_PRP_BASE(Private)   (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
 

Enumerations

enum  {
  BASEMEM_ASQ , BASEMEM_ACQ , BASEMEM_SQ , BASEMEM_CQ ,
  BASEMEM_PRP , MAX_BASEMEM_COUNT
}
 

Functions

EFI_STATUS NvmeMmioRead (IN OUT VOID *MemBuffer, IN UINTN MmioAddr, IN UINTN Size)
 
EFI_STATUS NvmeMmioWrite (IN OUT UINTN MmioAddr, IN VOID *MemBuffer, IN UINTN Size)
 
UINT32 NvmeBaseMemPageOffset (IN UINTN BaseMemIndex)
 
EFI_STATUS NvmeControllerInit (IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private)
 
EFI_STATUS NvmeIdentifyNamespace (IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private, IN UINT32 NamespaceId, IN VOID *Buffer)
 
VOID NvmeFreeDmaResource (IN PEI_NVME_CONTROLLER_PRIVATE_DATA *Private)
 

Detailed Description

The NvmExpressPei driver is used to manage non-volatile memory subsystem which follows NVM Express specification at PEI phase.

Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file NvmExpressPeiHci.h.

Macro Definition Documentation

◆ ALIGN

#define ALIGN (   v,
 
)    (UINTN)((((v) - 1) | ((a) - 1)) + 1)

Definition at line 46 of file NvmExpressPeiHci.h.

◆ NVME_ACQ_BASE

#define NVME_ACQ_BASE (   Private)    (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))

Definition at line 49 of file NvmExpressPeiHci.h.

◆ NVME_ASQ_BASE

#define NVME_ASQ_BASE (   Private)    (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))

Definition at line 48 of file NvmExpressPeiHci.h.

◆ NVME_CQ_BASE

#define NVME_CQ_BASE (   Private,
  Index 
)    (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))

Definition at line 51 of file NvmExpressPeiHci.h.

◆ NVME_GET_ACQ

#define NVME_GET_ACQ (   Private,
  Acq 
)    NvmeMmioRead (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))

Definition at line 25 of file NvmExpressPeiHci.h.

◆ NVME_GET_AQA

#define NVME_GET_AQA (   Private,
  Aqa 
)    NvmeMmioRead (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))

Definition at line 21 of file NvmExpressPeiHci.h.

◆ NVME_GET_ASQ

#define NVME_GET_ASQ (   Private,
  Asq 
)    NvmeMmioRead (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))

Definition at line 23 of file NvmExpressPeiHci.h.

◆ NVME_GET_CAP

#define NVME_GET_CAP (   Private,
  Cap 
)    NvmeMmioRead (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))

Definition at line 17 of file NvmExpressPeiHci.h.

◆ NVME_GET_CC

#define NVME_GET_CC (   Private,
  Cc 
)    NvmeMmioRead (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))

Definition at line 18 of file NvmExpressPeiHci.h.

◆ NVME_GET_CSTS

#define NVME_GET_CSTS (   Private,
  Csts 
)    NvmeMmioRead (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))

Definition at line 20 of file NvmExpressPeiHci.h.

◆ NVME_GET_VER

#define NVME_GET_VER (   Private,
  Ver 
)    NvmeMmioRead (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))

Definition at line 27 of file NvmExpressPeiHci.h.

◆ NVME_MEM_BASE

#define NVME_MEM_BASE (   Private)    ((UINTN)(Private->Buffer))

Definition at line 47 of file NvmExpressPeiHci.h.

◆ NVME_PRP_BASE

#define NVME_PRP_BASE (   Private)    (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))

Definition at line 52 of file NvmExpressPeiHci.h.

◆ NVME_SET_ACQ

#define NVME_SET_ACQ (   Private,
  Acq 
)    NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))

Definition at line 26 of file NvmExpressPeiHci.h.

◆ NVME_SET_AQA

#define NVME_SET_AQA (   Private,
  Aqa 
)    NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))

Definition at line 22 of file NvmExpressPeiHci.h.

◆ NVME_SET_ASQ

#define NVME_SET_ASQ (   Private,
  Asq 
)    NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))

Definition at line 24 of file NvmExpressPeiHci.h.

◆ NVME_SET_CC

#define NVME_SET_CC (   Private,
  Cc 
)    NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))

Definition at line 19 of file NvmExpressPeiHci.h.

◆ NVME_SET_CQHDBL

#define NVME_SET_CQHDBL (   Private,
  Qid,
  Cqhdbl 
)    NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))

Definition at line 29 of file NvmExpressPeiHci.h.

◆ NVME_SET_SQTDBL

#define NVME_SET_SQTDBL (   Private,
  Qid,
  Sqtdbl 
)    NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))

Definition at line 28 of file NvmExpressPeiHci.h.

◆ NVME_SQ_BASE

#define NVME_SQ_BASE (   Private,
  Index 
)    (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))

Definition at line 50 of file NvmExpressPeiHci.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Definition at line 34 of file NvmExpressPeiHci.h.

Function Documentation

◆ NvmeBaseMemPageOffset()

UINT32 NvmeBaseMemPageOffset ( IN UINTN  BaseMemIndex)

Get the page offset for specific NVME based memory.

Parameters
[in]BaseMemIndexThe Index of BaseMem (0-based).
Return values
-The page count for specific BaseMem Index

Definition at line 126 of file NvmExpressPeiHci.c.

◆ NvmeControllerInit()

EFI_STATUS NvmeControllerInit ( IN PEI_NVME_CONTROLLER_PRIVATE_DATA Private)

Initialize the Nvm Express controller.

Parameters
[in]PrivateThe pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
Return values
EFI_SUCCESSThe NVM Express Controller is initialized successfully.
OthersA device error occurred while initializing the controller.

Definition at line 553 of file NvmExpressPeiHci.c.

◆ NvmeFreeDmaResource()

VOID NvmeFreeDmaResource ( IN PEI_NVME_CONTROLLER_PRIVATE_DATA Private)

Free the DMA resources allocated by an NVME controller.

Parameters
[in]PrivateThe pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.

Definition at line 708 of file NvmExpressPeiHci.c.

◆ NvmeIdentifyNamespace()

EFI_STATUS NvmeIdentifyNamespace ( IN PEI_NVME_CONTROLLER_PRIVATE_DATA Private,
IN UINT32  NamespaceId,
IN VOID *  Buffer 
)

Get specified identify namespace data.

Parameters
[in]PrivateThe pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
[in]NamespaceIdThe specified namespace identifier.
[in]BufferThe buffer used to store the identify namespace data.
Returns
EFI_SUCCESS Successfully get the identify namespace data.
EFI_DEVICE_ERROR Fail to get the identify namespace data.

Definition at line 373 of file NvmExpressPeiHci.c.

◆ NvmeMmioRead()

EFI_STATUS NvmeMmioRead ( IN OUT VOID *  MemBuffer,
IN UINTN  MmioAddr,
IN UINTN  Size 
)

Transfer MMIO Data to memory.

Parameters
[in,out]MemBufferDestination: Memory address.
[in]MmioAddrSource: MMIO address.
[in]SizeSize for read.
Return values
EFI_SUCCESSMMIO read sucessfully.

Definition at line 24 of file NvmExpressPeiHci.c.

◆ NvmeMmioWrite()

EFI_STATUS NvmeMmioWrite ( IN OUT UINTN  MmioAddr,
IN VOID *  MemBuffer,
IN UINTN  Size 
)

Transfer memory data to MMIO.

Parameters
[in,out]MmioAddrDestination: MMIO address.
[in]MemBufferSource: Memory address.
[in]SizeSize for write.
Return values
EFI_SUCCESSMMIO write sucessfully.

Definition at line 76 of file NvmExpressPeiHci.c.