P6Msr.h

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#ifndef __P6_MSR_H__
#define __P6_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x03 || \
    DisplayModel == 0x05 || \
    DisplayModel == 0x07 || \
    DisplayModel == 0x08 || \
    DisplayModel == 0x0A || \
    DisplayModel == 0x0B \
    ) \
   )
 
#define MSR_P6_P5_MC_ADDR  0x00000000
 
#define MSR_P6_P5_MC_TYPE  0x00000001
 
#define MSR_P6_TSC  0x00000010
 
#define MSR_P6_IA32_PLATFORM_ID  0x00000017
 
typedef union {
  struct {
    UINT32    Reserved1 : 32;
    UINT32    Reserved2 : 18;
    UINT32    PlatformId              : 3;
    UINT32    L2CacheLatencyRead      : 4;
    UINT32    Reserved3               : 3;
    UINT32    ClockFrequencyRatioRead : 1;
    UINT32    Reserved4               : 3;
  } Bits;
  UINT64    Uint64;
} MSR_P6_IA32_PLATFORM_ID_REGISTER;
 
#define MSR_P6_APIC_BASE  0x0000001B
 
typedef union {
  struct {
    UINT32    Reserved1 : 8;
    UINT32    BSP       : 1;
    UINT32    Reserved2 : 2;
    UINT32    EN        : 1;
    UINT32    ApicBase  : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_APIC_BASE_REGISTER;
 
#define MSR_P6_EBL_CR_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    Reserved1                   : 1;
    UINT32    DataErrorCheckingEnable     : 1;
    UINT32    ResponseErrorCheckingEnable : 1;
    UINT32    AERR_DriveEnable            : 1;
    UINT32    BERR_Enable                 : 1;
    UINT32    Reserved2                   : 1;
    UINT32    BERR_DriverEnable           : 1;
    UINT32    BINIT_DriverEnable          : 1;
    UINT32    OutputTriStateEnable        : 1;
    UINT32    ExecuteBIST                 : 1;
    UINT32    AERR_ObservationEnabled     : 1;
    UINT32    Reserved3                   : 1;
    UINT32    BINIT_ObservationEnabled    : 1;
    UINT32    InOrderQueueDepth           : 1;
    UINT32    ResetVector                 : 1;
    UINT32    FRCModeEnable               : 1;
    UINT32    APICClusterID               : 2;
    UINT32    SystemBusFrequency          : 2;
    UINT32    SymmetricArbitrationID      : 2;
    UINT32    ClockFrequencyRatio         : 4;
    UINT32    LowPowerModeEnable          : 1;
    UINT32    ClockFrequencyRatio1        : 1;
    UINT32    Reserved4                   : 4;
    UINT32    Reserved5                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_EBL_CR_POWERON_REGISTER;
 
#define MSR_P6_TEST_CTL  0x00000033
 
typedef union {
  struct {
    UINT32    Reserved1              : 30;
    UINT32    StreamingBufferDisable : 1;
    UINT32    Disable_LOCK           : 1;
    UINT32    Reserved2              : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_TEST_CTL_REGISTER;
 
#define MSR_P6_BIOS_UPDT_TRIG  0x00000079
 
#define MSR_P6_BBL_CR_D0  0x00000088
#define MSR_P6_BBL_CR_D1  0x00000089
#define MSR_P6_BBL_CR_D2  0x0000008A
 
#define MSR_P6_BIOS_SIGN  0x0000008B
 
#define MSR_P6_PERFCTR0  0x000000C1
#define MSR_P6_PERFCTR1  0x000000C2
 
#define MSR_P6_MTRRCAP  0x000000FE
 
#define MSR_P6_BBL_CR_ADDR  0x00000116
 
typedef union {
  struct {
    UINT32    Reserved1 : 3;
    UINT32    Address   : 29;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_BBL_CR_ADDR_REGISTER;
 
#define MSR_P6_BBL_CR_DECC  0x00000118
 
#define MSR_P6_BBL_CR_CTL  0x00000119
 
typedef union {
  struct {
    UINT32    L2Command       : 5;
    UINT32    StateToL2       : 2;
    UINT32    Reserved        : 1;
    UINT32    WayToL2         : 2;
    UINT32    Way             : 2;
    UINT32    MESI            : 2;
    UINT32    StateFromL2     : 2;
    UINT32    Reserved2       : 1;
    UINT32    L2Hit           : 1;
    UINT32    Reserved3       : 1;
    UINT32    UserEcc         : 2;
    UINT32    ProcessorNumber : 1;
    UINT32    Reserved4       : 10;
    UINT32    Reserved5       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_BBL_CR_CTL_REGISTER;
 
#define MSR_P6_BBL_CR_TRIG  0x0000011A
 
#define MSR_P6_BBL_CR_BUSY  0x0000011B
 
#define MSR_P6_BBL_CR_CTL3  0x0000011E
 
typedef union {
  struct {
    UINT32    L2Configured             : 1;
    UINT32    L2CacheLatency           : 4;
    UINT32    ECCCheckEnable           : 1;
    UINT32    AddressParityCheckEnable : 1;
    UINT32    CRTNParityCheckEnable    : 1;
    UINT32    L2Enabled                : 1;
    UINT32    L2Associativity          : 2;
    UINT32    L2Banks                  : 2;
    UINT32    CacheSizePerBank         : 5;
    UINT32    CacheStateErrorEnable    : 1;
    UINT32    Reserved1                : 1;
    UINT32    L2AddressRange           : 3;
    UINT32    L2HardwareDisable        : 1;
    UINT32    Reserved2                : 1;
    UINT32    CacheBusFraction         : 1;
    UINT32    Reserved3                : 6;
    UINT32    Reserved4                : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_BBL_CR_CTL3_REGISTER;
 
#define MSR_P6_SYSENTER_CS_MSR  0x00000174
 
#define MSR_P6_SYSENTER_ESP_MSR  0x00000175
 
#define MSR_P6_SYSENTER_EIP_MSR  0x00000176
 
#define MSR_P6_MCG_CAP  0x00000179
 
#define MSR_P6_MCG_STATUS  0x0000017A
 
#define MSR_P6_MCG_CTL  0x0000017B
 
#define MSR_P6_PERFEVTSEL0  0x00000186
#define MSR_P6_PERFEVTSEL1  0x00000187
 
typedef union {
  struct {
    UINT32    EventSelect : 8;
    UINT32    UMASK       : 8;
    UINT32    USR         : 1;
    UINT32    OS          : 1;
    UINT32    E           : 1;
    UINT32    PC          : 1;
    UINT32    INT         : 1;
    UINT32    Reserved1   : 1;
    UINT32    EN          : 1;
    UINT32    INV         : 1;
    UINT32    CMASK       : 8;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_PERFEVTSEL_REGISTER;
 
#define MSR_P6_DEBUGCTLMSR  0x000001D9
 
typedef union {
  struct {
    UINT32    LBR       : 1;
    UINT32    BTF       : 1;
    UINT32    PB0       : 1;
    UINT32    PB1       : 1;
    UINT32    PB2       : 1;
    UINT32    PB3       : 1;
    UINT32    TR        : 1;
    UINT32    Reserved1 : 25;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_DEBUGCTLMSR_REGISTER;
 
#define MSR_P6_LASTBRANCHFROMIP  0x000001DB
 
#define MSR_P6_LASTBRANCHTOIP  0x000001DC
 
#define MSR_P6_LASTINTFROMIP  0x000001DD
 
#define MSR_P6_LASTINTTOIP  0x000001DE
 
#define MSR_P6_MTRRPHYSBASE0  0x00000200
#define MSR_P6_MTRRPHYSBASE1  0x00000202
#define MSR_P6_MTRRPHYSBASE2  0x00000204
#define MSR_P6_MTRRPHYSBASE3  0x00000206
#define MSR_P6_MTRRPHYSBASE4  0x00000208
#define MSR_P6_MTRRPHYSBASE5  0x0000020A
#define MSR_P6_MTRRPHYSBASE6  0x0000020C
#define MSR_P6_MTRRPHYSBASE7  0x0000020E
 
#define MSR_P6_MTRRPHYSMASK0  0x00000201
#define MSR_P6_MTRRPHYSMASK1  0x00000203
#define MSR_P6_MTRRPHYSMASK2  0x00000205
#define MSR_P6_MTRRPHYSMASK3  0x00000207
#define MSR_P6_MTRRPHYSMASK4  0x00000209
#define MSR_P6_MTRRPHYSMASK5  0x0000020B
#define MSR_P6_MTRRPHYSMASK6  0x0000020D
#define MSR_P6_MTRRPHYSMASK7  0x0000020F
 
#define MSR_P6_MTRRFIX64K_00000  0x00000250
 
#define MSR_P6_MTRRFIX16K_80000  0x00000258
 
#define MSR_P6_MTRRFIX16K_A0000  0x00000259
 
#define MSR_P6_MTRRFIX4K_C0000  0x00000268
 
#define MSR_P6_MTRRFIX4K_C8000  0x00000269
 
#define MSR_P6_MTRRFIX4K_D0000  0x0000026A
 
#define MSR_P6_MTRRFIX4K_D8000  0x0000026B
 
#define MSR_P6_MTRRFIX4K_E0000  0x0000026C
 
#define MSR_P6_MTRRFIX4K_E8000  0x0000026D
 
#define MSR_P6_MTRRFIX4K_F0000  0x0000026E
 
#define MSR_P6_MTRRFIX4K_F8000  0x0000026F
 
#define MSR_P6_MTRRDEFTYPE  0x000002FF
 
typedef union {
  struct {
    UINT32    Type      : 3;
    UINT32    Reserved1 : 7;
    UINT32    FE        : 1;
    UINT32    E         : 1;
    UINT32    Reserved2 : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_P6_MTRRDEFTYPE_REGISTER;
 
#define MSR_P6_MC0_CTL  0x00000400
#define MSR_P6_MC1_CTL  0x00000404
#define MSR_P6_MC2_CTL  0x00000408
#define MSR_P6_MC3_CTL  0x00000410
#define MSR_P6_MC4_CTL  0x0000040C
 
#define MSR_P6_MC0_STATUS  0x00000401
#define MSR_P6_MC1_STATUS  0x00000405
#define MSR_P6_MC2_STATUS  0x00000409
#define MSR_P6_MC3_STATUS  0x00000411
#define MSR_P6_MC4_STATUS  0x0000040D
 
typedef union {
  struct {
    UINT32    MC_STATUS_MCACOD : 16;
    UINT32    MC_STATUS_MSCOD  : 16;
    UINT32    Reserved         : 25;
    UINT32    MC_STATUS_DAM    : 1;
    UINT32    MC_STATUS_ADDRV  : 1;
    UINT32    MC_STATUS_MISCV  : 1;
    UINT32    MC_STATUS_EN     : 1;
    UINT32    MC_STATUS_UC     : 1;
    UINT32    MC_STATUS_O      : 1;
    UINT32    MC_STATUS_V      : 1;
  } Bits;
  UINT64    Uint64;
} MSR_P6_MC_STATUS_REGISTER;
 
#define MSR_P6_MC0_ADDR  0x00000402
#define MSR_P6_MC1_ADDR  0x00000406
#define MSR_P6_MC2_ADDR  0x0000040A
#define MSR_P6_MC3_ADDR  0x00000412
#define MSR_P6_MC4_ADDR  0x0000040E
 
#define MSR_P6_MC0_MISC  0x00000403
#define MSR_P6_MC1_MISC  0x00000407
#define MSR_P6_MC2_MISC  0x0000040B
#define MSR_P6_MC3_MISC  0x00000413
#define MSR_P6_MC4_MISC  0x0000040F
 
#endif