TianoCore EDK2 master
P6Msr.h
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1
18#ifndef __P6_MSR_H__
19#define __P6_MSR_H__
20
22
32#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x03 || \
36 DisplayModel == 0x05 || \
37 DisplayModel == 0x07 || \
38 DisplayModel == 0x08 || \
39 DisplayModel == 0x0A || \
40 DisplayModel == 0x0B \
41 ) \
42 )
43
60#define MSR_P6_P5_MC_ADDR 0x00000000
61
78#define MSR_P6_P5_MC_TYPE 0x00000001
79
96#define MSR_P6_TSC 0x00000010
97
116#define MSR_P6_IA32_PLATFORM_ID 0x00000017
117
121typedef union {
125 struct {
126 UINT32 Reserved1 : 32;
127 UINT32 Reserved2 : 18;
142 UINT32 PlatformId : 3;
147 UINT32 Reserved3 : 3;
152 UINT32 Reserved4 : 3;
153 } Bits;
157 UINT64 Uint64;
159
178#define MSR_P6_APIC_BASE 0x0000001B
179
183typedef union {
187 struct {
188 UINT32 Reserved1 : 8;
192 UINT32 BSP : 1;
193 UINT32 Reserved2 : 2;
198 UINT32 EN : 1;
202 UINT32 ApicBase : 20;
203 UINT32 Reserved3 : 32;
204 } Bits;
208 UINT32 Uint32;
212 UINT64 Uint64;
214
234#define MSR_P6_EBL_CR_POWERON 0x0000002A
235
239typedef union {
243 struct {
244 UINT32 Reserved1 : 1;
262 UINT32 BERR_Enable : 1;
263 UINT32 Reserved2 : 1;
280 UINT32 ExecuteBIST : 1;
285 UINT32 Reserved3 : 1;
297 UINT32 ResetVector : 1;
301 UINT32 FRCModeEnable : 1;
305 UINT32 APICClusterID : 2;
327 UINT32 Reserved4 : 4;
328 UINT32 Reserved5 : 32;
329 } Bits;
333 UINT32 Uint32;
337 UINT64 Uint64;
339
358#define MSR_P6_TEST_CTL 0x00000033
359
363typedef union {
367 struct {
368 UINT32 Reserved1 : 30;
376 UINT32 Disable_LOCK : 1;
377 UINT32 Reserved2 : 32;
378 } Bits;
382 UINT32 Uint32;
386 UINT64 Uint64;
388
405#define MSR_P6_BIOS_UPDT_TRIG 0x00000079
406
426#define MSR_P6_BBL_CR_D0 0x00000088
427#define MSR_P6_BBL_CR_D1 0x00000089
428#define MSR_P6_BBL_CR_D2 0x0000008A
430
448#define MSR_P6_BIOS_SIGN 0x0000008B
449
468#define MSR_P6_PERFCTR0 0x000000C1
469#define MSR_P6_PERFCTR1 0x000000C2
471
488#define MSR_P6_MTRRCAP 0x000000FE
489
509#define MSR_P6_BBL_CR_ADDR 0x00000116
510
514typedef union {
518 struct {
519 UINT32 Reserved1 : 3;
523 UINT32 Address : 29;
524 UINT32 Reserved2 : 32;
525 } Bits;
529 UINT32 Uint32;
533 UINT64 Uint64;
535
552#define MSR_P6_BBL_CR_DECC 0x00000118
553
573#define MSR_P6_BBL_CR_CTL 0x00000119
574
578typedef union {
582 struct {
594 UINT32 L2Command : 5;
598 UINT32 StateToL2 : 2;
599 UINT32 Reserved : 1;
603 UINT32 WayToL2 : 2;
607 UINT32 Way : 2;
611 UINT32 MESI : 2;
615 UINT32 StateFromL2 : 2;
616 UINT32 Reserved2 : 1;
620 UINT32 L2Hit : 1;
621 UINT32 Reserved3 : 1;
625 UINT32 UserEcc : 2;
629 UINT32 ProcessorNumber : 1;
630 UINT32 Reserved4 : 10;
631 UINT32 Reserved5 : 32;
632 } Bits;
636 UINT32 Uint32;
640 UINT64 Uint64;
642
660#define MSR_P6_BBL_CR_TRIG 0x0000011A
661
679#define MSR_P6_BBL_CR_BUSY 0x0000011B
680
699#define MSR_P6_BBL_CR_CTL3 0x0000011E
700
704typedef union {
708 struct {
712 UINT32 L2Configured : 1;
716 UINT32 L2CacheLatency : 4;
720 UINT32 ECCCheckEnable : 1;
732 UINT32 L2Enabled : 1;
737 UINT32 L2Associativity : 2;
741 UINT32 L2Banks : 2;
751 UINT32 Reserved1 : 1;
756 UINT32 L2AddressRange : 3;
761 UINT32 Reserved2 : 1;
766 UINT32 Reserved3 : 6;
767 UINT32 Reserved4 : 32;
768 } Bits;
772 UINT32 Uint32;
776 UINT64 Uint64;
778
795#define MSR_P6_SYSENTER_CS_MSR 0x00000174
796
813#define MSR_P6_SYSENTER_ESP_MSR 0x00000175
814
831#define MSR_P6_SYSENTER_EIP_MSR 0x00000176
832
849#define MSR_P6_MCG_CAP 0x00000179
850
867#define MSR_P6_MCG_STATUS 0x0000017A
868
885#define MSR_P6_MCG_CTL 0x0000017B
886
907#define MSR_P6_PERFEVTSEL0 0x00000186
908#define MSR_P6_PERFEVTSEL1 0x00000187
910
915typedef union {
919 struct {
924 UINT32 EventSelect : 8;
929 UINT32 UMASK : 8;
934 UINT32 USR : 1;
938 UINT32 OS : 1;
942 UINT32 E : 1;
947 UINT32 PC : 1;
952 UINT32 INT : 1;
953 UINT32 Reserved1 : 1;
958 UINT32 EN : 1;
963 UINT32 INV : 1;
967 UINT32 CMASK : 8;
968 UINT32 Reserved2 : 32;
969 } Bits;
973 UINT32 Uint32;
977 UINT64 Uint64;
979
998#define MSR_P6_DEBUGCTLMSR 0x000001D9
999
1003typedef union {
1007 struct {
1011 UINT32 LBR : 1;
1015 UINT32 BTF : 1;
1019 UINT32 PB0 : 1;
1023 UINT32 PB1 : 1;
1027 UINT32 PB2 : 1;
1031 UINT32 PB3 : 1;
1035 UINT32 TR : 1;
1036 UINT32 Reserved1 : 25;
1037 UINT32 Reserved2 : 32;
1038 } Bits;
1042 UINT32 Uint32;
1046 UINT64 Uint64;
1048
1065#define MSR_P6_LASTBRANCHFROMIP 0x000001DB
1066
1083#define MSR_P6_LASTBRANCHTOIP 0x000001DC
1084
1101#define MSR_P6_LASTINTFROMIP 0x000001DD
1102
1119#define MSR_P6_LASTINTTOIP 0x000001DE
1120
1145#define MSR_P6_MTRRPHYSBASE0 0x00000200
1146#define MSR_P6_MTRRPHYSBASE1 0x00000202
1147#define MSR_P6_MTRRPHYSBASE2 0x00000204
1148#define MSR_P6_MTRRPHYSBASE3 0x00000206
1149#define MSR_P6_MTRRPHYSBASE4 0x00000208
1150#define MSR_P6_MTRRPHYSBASE5 0x0000020A
1151#define MSR_P6_MTRRPHYSBASE6 0x0000020C
1152#define MSR_P6_MTRRPHYSBASE7 0x0000020E
1154
1179#define MSR_P6_MTRRPHYSMASK0 0x00000201
1180#define MSR_P6_MTRRPHYSMASK1 0x00000203
1181#define MSR_P6_MTRRPHYSMASK2 0x00000205
1182#define MSR_P6_MTRRPHYSMASK3 0x00000207
1183#define MSR_P6_MTRRPHYSMASK4 0x00000209
1184#define MSR_P6_MTRRPHYSMASK5 0x0000020B
1185#define MSR_P6_MTRRPHYSMASK6 0x0000020D
1186#define MSR_P6_MTRRPHYSMASK7 0x0000020F
1188
1205#define MSR_P6_MTRRFIX64K_00000 0x00000250
1206
1223#define MSR_P6_MTRRFIX16K_80000 0x00000258
1224
1241#define MSR_P6_MTRRFIX16K_A0000 0x00000259
1242
1259#define MSR_P6_MTRRFIX4K_C0000 0x00000268
1260
1277#define MSR_P6_MTRRFIX4K_C8000 0x00000269
1278
1295#define MSR_P6_MTRRFIX4K_D0000 0x0000026A
1296
1313#define MSR_P6_MTRRFIX4K_D8000 0x0000026B
1314
1331#define MSR_P6_MTRRFIX4K_E0000 0x0000026C
1332
1349#define MSR_P6_MTRRFIX4K_E8000 0x0000026D
1350
1367#define MSR_P6_MTRRFIX4K_F0000 0x0000026E
1368
1385#define MSR_P6_MTRRFIX4K_F8000 0x0000026F
1386
1405#define MSR_P6_MTRRDEFTYPE 0x000002FF
1406
1410typedef union {
1414 struct {
1418 UINT32 Type : 3;
1419 UINT32 Reserved1 : 7;
1423 UINT32 FE : 1;
1427 UINT32 E : 1;
1428 UINT32 Reserved2 : 20;
1429 UINT32 Reserved3 : 32;
1430 } Bits;
1434 UINT32 Uint32;
1438 UINT64 Uint64;
1440
1462#define MSR_P6_MC0_CTL 0x00000400
1463#define MSR_P6_MC1_CTL 0x00000404
1464#define MSR_P6_MC2_CTL 0x00000408
1465#define MSR_P6_MC3_CTL 0x00000410
1466#define MSR_P6_MC4_CTL 0x0000040C
1468
1494#define MSR_P6_MC0_STATUS 0x00000401
1495#define MSR_P6_MC1_STATUS 0x00000405
1496#define MSR_P6_MC2_STATUS 0x00000409
1497#define MSR_P6_MC3_STATUS 0x00000411
1498#define MSR_P6_MC4_STATUS 0x0000040D
1500
1505typedef union {
1509 struct {
1513 UINT32 MC_STATUS_MCACOD : 16;
1517 UINT32 MC_STATUS_MSCOD : 16;
1518 UINT32 Reserved : 25;
1522 UINT32 MC_STATUS_DAM : 1;
1535 UINT32 MC_STATUS_EN : 1;
1539 UINT32 MC_STATUS_UC : 1;
1543 UINT32 MC_STATUS_O : 1;
1547 UINT32 MC_STATUS_V : 1;
1548 } Bits;
1552 UINT64 Uint64;
1554
1577#define MSR_P6_MC0_ADDR 0x00000402
1578#define MSR_P6_MC1_ADDR 0x00000406
1579#define MSR_P6_MC2_ADDR 0x0000040A
1580#define MSR_P6_MC3_ADDR 0x00000412
1581#define MSR_P6_MC4_ADDR 0x0000040E
1583
1605#define MSR_P6_MC0_MISC 0x00000403
1606#define MSR_P6_MC1_MISC 0x00000407
1607#define MSR_P6_MC2_MISC 0x0000040B
1608#define MSR_P6_MC3_MISC 0x00000413
1609#define MSR_P6_MC4_MISC 0x0000040F
1611
1612#endif
UINT32 AddressParityCheckEnable
Definition: P6Msr.h:724
UINT32 StreamingBufferDisable
Definition: P6Msr.h:372