#include <PiDxe.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciIo.h>
#include <Protocol/LoadFile2.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PciHotPlugRequest.h>
#include <Protocol/DevicePath.h>
#include <Protocol/PciPlatform.h>
#include <Protocol/PciHotPlugInit.h>
#include <Protocol/Decompress.h>
#include <Protocol/BusSpecificDriverOverride.h>
#include <Protocol/IncompatiblePciDeviceSupport.h>
#include <Protocol/PciOverride.h>
#include <Protocol/PciEnumerationComplete.h>
#include <Protocol/IoMmu.h>
#include <Protocol/DeviceSecurity.h>
#include <Library/DebugLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/BaseLib.h>
#include <Library/UefiLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DevicePathLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/PeImage.h>
#include <IndustryStandard/Acpi.h>
#include "ComponentName.h"
#include "PciIo.h"
#include "PciCommand.h"
#include "PciDeviceSupport.h"
#include "PciEnumerator.h"
#include "PciEnumeratorSupport.h"
#include "PciDriverOverride.h"
#include "PciRomTable.h"
#include "PciOptionRomSupport.h"
#include "PciPowerManagement.h"
#include "PciHotPlugSupport.h"
#include "PciLib.h"

Data Structures
struct	_PCI_BAR

struct	_PCI_IO_DEVICE

Macros
#define	EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)

#define	EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)

#define	EFI_PCI_IOV_POLICY_ARI 0x0001

#define	EFI_PCI_IOV_POLICY_SRIOV 0x0002

#define	EFI_PCI_IOV_POLICY_MRIOV 0x0004

#define	VGABASE1 0x3B0

#define	VGALIMIT1 0x3BB

#define	VGABASE2 0x3C0

#define	VGALIMIT2 0x3DF

#define	ISABASE 0x100

#define	ISALIMIT 0x3FF

#define	PCI_CARD_MEMORY_BASE_0 0x1C

#define	PCI_CARD_MEMORY_LIMIT_0 0x20

#define	PCI_CARD_MEMORY_BASE_1 0x24

#define	PCI_CARD_MEMORY_LIMIT_1 0x28

#define	PCI_CARD_IO_BASE_0_LOWER 0x2C

#define	PCI_CARD_IO_BASE_0_UPPER 0x2E

#define	PCI_CARD_IO_LIMIT_0_LOWER 0x30

#define	PCI_CARD_IO_LIMIT_0_UPPER 0x32

#define	PCI_CARD_IO_BASE_1_LOWER 0x34

#define	PCI_CARD_IO_BASE_1_UPPER 0x36

#define	PCI_CARD_IO_LIMIT_1_LOWER 0x38

#define	PCI_CARD_IO_LIMIT_1_UPPER 0x3A

#define	PCI_CARD_BRIDGE_CONTROL 0x3E

#define	PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8

#define	PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9

#define	RB_IO_RANGE 1

#define	RB_MEM32_RANGE 2

#define	RB_PMEM32_RANGE 3

#define	RB_MEM64_RANGE 4

#define	RB_PMEM64_RANGE 5

#define	PPB_BAR_0 0

#define	PPB_BAR_1 1

#define	PPB_IO_RANGE 2

#define	PPB_MEM32_RANGE 3

#define	PPB_PMEM32_RANGE 4

#define	PPB_PMEM64_RANGE 5

#define	PPB_MEM64_RANGE 0xFF

#define	P2C_BAR_0 0

#define	P2C_MEM_1 1

#define	P2C_MEM_2 2

#define	P2C_IO_1 3

#define	P2C_IO_2 4

#define	EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001

#define	EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002

#define	EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004

#define	EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008

#define	EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010

#define	EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020

#define	EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040

#define	PCI_MAX_HOST_BRIDGE_NUM 0x0010

#define	EFI_SET_SUPPORTS 0

#define	EFI_SET_ATTRIBUTES 1

#define	PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')

#define	PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)

#define	PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)

#define	PCI_IO_DEVICE_FROM_LINK(a) CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)

#define	PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)

#define	IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)

Typedefs
typedef struct _PCI_IO_DEVICE	PCI_IO_DEVICE

typedef struct _PCI_BAR	PCI_BAR

Enumerations
enum	PCI_BAR_TYPE { PciBarTypeUnknown = 0 , PciBarTypeIo16 , PciBarTypeIo32 , PciBarTypeMem32 , PciBarTypePMem32 , PciBarTypeMem64 , PciBarTypePMem64 , PciBarTypeOpRom , PciBarTypeIo , PciBarTypeMem , PciBarTypeMaxType }

Functions
EFI_STATUS EFIAPI	PciBusDriverBindingSupported (IN EFI_DRIVER_BINDING_PROTOCOL This, IN EFI_HANDLE Controller, IN EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath)

EFI_STATUS EFIAPI	PciBusDriverBindingStart (IN EFI_DRIVER_BINDING_PROTOCOL This, IN EFI_HANDLE Controller, IN EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath)

EFI_STATUS EFIAPI	PciBusDriverBindingStop (IN EFI_DRIVER_BINDING_PROTOCOL This, IN EFI_HANDLE Controller, IN UINTN NumberOfChildren, IN EFI_HANDLE ChildHandleBuffer)

Variables
EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *	gIncompatiblePciDeviceSupport

EFI_DRIVER_BINDING_PROTOCOL	gPciBusDriverBinding

EFI_COMPONENT_NAME_PROTOCOL	gPciBusComponentName

EFI_COMPONENT_NAME2_PROTOCOL	gPciBusComponentName2

BOOLEAN	gFullEnumeration

UINTN	gPciHostBridgeNumber

EFI_HANDLE	gPciHostBrigeHandles [PCI_MAX_HOST_BRIDGE_NUM]

UINT64	gAllOne

UINT64	gAllZero

EFI_PCI_PLATFORM_PROTOCOL *	gPciPlatformProtocol

EFI_PCI_OVERRIDE_PROTOCOL *	gPciOverrideProtocol

BOOLEAN	mReserveIsaAliases

BOOLEAN	mReserveVgaAliases

Detailed Description

Header files and data structures needed by PCI Bus module.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file PciBus.h.

Macro Definition Documentation

◆ EFI_BRIDGE_IO16_DECODE_SUPPORTED

#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008

Definition at line 147 of file PciBus.h.

◆ EFI_BRIDGE_IO32_DECODE_SUPPORTED

#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001

Definition at line 144 of file PciBus.h.

◆ EFI_BRIDGE_MEM32_DECODE_SUPPORTED

#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040

Definition at line 150 of file PciBus.h.

◆ EFI_BRIDGE_MEM64_DECODE_SUPPORTED

#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020

Definition at line 149 of file PciBus.h.

◆ EFI_BRIDGE_PMEM32_DECODE_SUPPORTED

#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002

Definition at line 145 of file PciBus.h.

◆ EFI_BRIDGE_PMEM64_DECODE_SUPPORTED

#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004

Definition at line 146 of file PciBus.h.

◆ EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED

#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010

Definition at line 148 of file PciBus.h.

◆ EFI_PCI_BUS_OF_RID

#define EFI_PCI_BUS_OF_RID ( RID ) ((UINT32)RID >> 8)

Definition at line 50 of file PciBus.h.

◆ EFI_PCI_IOV_POLICY_ARI

#define EFI_PCI_IOV_POLICY_ARI 0x0001

Definition at line 52 of file PciBus.h.

◆ EFI_PCI_IOV_POLICY_MRIOV

#define EFI_PCI_IOV_POLICY_MRIOV 0x0004

Definition at line 54 of file PciBus.h.

◆ EFI_PCI_IOV_POLICY_SRIOV

#define EFI_PCI_IOV_POLICY_SRIOV 0x0002

Definition at line 53 of file PciBus.h.

◆ EFI_PCI_RID

#define EFI_PCI_RID	(	Bus,
		Device,
		Function
	)	(((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)

Definition at line 49 of file PciBus.h.

◆ EFI_SET_ATTRIBUTES

#define EFI_SET_ATTRIBUTES 1

Definition at line 158 of file PciBus.h.

◆ EFI_SET_SUPPORTS

#define EFI_SET_SUPPORTS 0

Definition at line 157 of file PciBus.h.

◆ IS_PCI_GFX

#define IS_PCI_GFX ( _p ) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)

Macro that checks whether device is a GFX device.

Parameters

_p	Specified device.

Return values

TRUE	Device is a GFX device.
FALSE	Device is not a GFX device.

Definition at line 325 of file PciBus.h.

◆ ISABASE

#define ISABASE 0x100

Definition at line 89 of file PciBus.h.

◆ ISALIMIT

#define ISALIMIT 0x3FF

Definition at line 90 of file PciBus.h.

◆ P2C_BAR_0

#define P2C_BAR_0 0

Definition at line 138 of file PciBus.h.

◆ P2C_IO_1

#define P2C_IO_1 3

Definition at line 141 of file PciBus.h.

◆ P2C_IO_2

#define P2C_IO_2 4

Definition at line 142 of file PciBus.h.

◆ P2C_MEM_1

#define P2C_MEM_1 1

Definition at line 139 of file PciBus.h.

◆ P2C_MEM_2

#define P2C_MEM_2 2

Definition at line 140 of file PciBus.h.

◆ PCI_CARD_BRIDGE_CONTROL

#define PCI_CARD_BRIDGE_CONTROL 0x3E

Definition at line 119 of file PciBus.h.

◆ PCI_CARD_IO_BASE_0_LOWER

#define PCI_CARD_IO_BASE_0_LOWER 0x2C

Definition at line 111 of file PciBus.h.

◆ PCI_CARD_IO_BASE_0_UPPER

#define PCI_CARD_IO_BASE_0_UPPER 0x2E

Definition at line 112 of file PciBus.h.

◆ PCI_CARD_IO_BASE_1_LOWER

#define PCI_CARD_IO_BASE_1_LOWER 0x34

Definition at line 115 of file PciBus.h.

◆ PCI_CARD_IO_BASE_1_UPPER

#define PCI_CARD_IO_BASE_1_UPPER 0x36

Definition at line 116 of file PciBus.h.

◆ PCI_CARD_IO_LIMIT_0_LOWER

#define PCI_CARD_IO_LIMIT_0_LOWER 0x30

Definition at line 113 of file PciBus.h.

◆ PCI_CARD_IO_LIMIT_0_UPPER

#define PCI_CARD_IO_LIMIT_0_UPPER 0x32

Definition at line 114 of file PciBus.h.

◆ PCI_CARD_IO_LIMIT_1_LOWER

#define PCI_CARD_IO_LIMIT_1_LOWER 0x38

Definition at line 117 of file PciBus.h.

◆ PCI_CARD_IO_LIMIT_1_UPPER

#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A

Definition at line 118 of file PciBus.h.

◆ PCI_CARD_MEMORY_BASE_0

#define PCI_CARD_MEMORY_BASE_0 0x1C

Definition at line 107 of file PciBus.h.

◆ PCI_CARD_MEMORY_BASE_1

#define PCI_CARD_MEMORY_BASE_1 0x24

Definition at line 109 of file PciBus.h.

◆ PCI_CARD_MEMORY_LIMIT_0

#define PCI_CARD_MEMORY_LIMIT_0 0x20

Definition at line 108 of file PciBus.h.

◆ PCI_CARD_MEMORY_LIMIT_1

#define PCI_CARD_MEMORY_LIMIT_1 0x28

Definition at line 110 of file PciBus.h.

◆ PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE

#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8

Definition at line 121 of file PciBus.h.

◆ PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE

#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9

Definition at line 122 of file PciBus.h.

◆ PCI_IO_DEVICE_FROM_LINK

#define PCI_IO_DEVICE_FROM_LINK ( a ) CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)

Definition at line 293 of file PciBus.h.

◆ PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS

#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS ( a ) CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)

Definition at line 296 of file PciBus.h.

◆ PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS

#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS ( a ) CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)

Definition at line 290 of file PciBus.h.

◆ PCI_IO_DEVICE_FROM_PCI_IO_THIS

#define PCI_IO_DEVICE_FROM_PCI_IO_THIS ( a ) CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)

Definition at line 287 of file PciBus.h.

◆ PCI_IO_DEVICE_SIGNATURE

#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')

Definition at line 160 of file PciBus.h.

◆ PCI_MAX_HOST_BRIDGE_NUM

#define PCI_MAX_HOST_BRIDGE_NUM 0x0010

Definition at line 152 of file PciBus.h.

◆ PPB_BAR_0

#define PPB_BAR_0 0

Definition at line 130 of file PciBus.h.

◆ PPB_BAR_1

#define PPB_BAR_1 1

Definition at line 131 of file PciBus.h.

◆ PPB_IO_RANGE

#define PPB_IO_RANGE 2

Definition at line 132 of file PciBus.h.

◆ PPB_MEM32_RANGE

#define PPB_MEM32_RANGE 3

Definition at line 133 of file PciBus.h.

◆ PPB_MEM64_RANGE

#define PPB_MEM64_RANGE 0xFF

Definition at line 136 of file PciBus.h.

◆ PPB_PMEM32_RANGE

#define PPB_PMEM32_RANGE 4

Definition at line 134 of file PciBus.h.

◆ PPB_PMEM64_RANGE

#define PPB_PMEM64_RANGE 5

Definition at line 135 of file PciBus.h.

◆ RB_IO_RANGE

#define RB_IO_RANGE 1

Definition at line 124 of file PciBus.h.

◆ RB_MEM32_RANGE

#define RB_MEM32_RANGE 2

Definition at line 125 of file PciBus.h.

◆ RB_MEM64_RANGE

#define RB_MEM64_RANGE 4

Definition at line 127 of file PciBus.h.

◆ RB_PMEM32_RANGE

#define RB_PMEM32_RANGE 3

Definition at line 126 of file PciBus.h.

◆ RB_PMEM64_RANGE

#define RB_PMEM64_RANGE 5

Definition at line 128 of file PciBus.h.

◆ VGABASE1

#define VGABASE1 0x3B0

Definition at line 83 of file PciBus.h.

◆ VGABASE2

#define VGABASE2 0x3C0

Definition at line 86 of file PciBus.h.

◆ VGALIMIT1

#define VGALIMIT1 0x3BB

Definition at line 84 of file PciBus.h.

◆ VGALIMIT2

#define VGALIMIT2 0x3DF

Definition at line 87 of file PciBus.h.

Typedef Documentation

◆ PCI_BAR

typedef struct _PCI_BAR PCI_BAR

Definition at line 47 of file PciBus.h.

◆ PCI_IO_DEVICE

typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE

Definition at line 46 of file PciBus.h.

Enumeration Type Documentation

◆ PCI_BAR_TYPE

enum PCI_BAR_TYPE

Definition at line 56 of file PciBus.h.

Function Documentation

◆ PciBusDriverBindingStart()

EFI_STATUS EFIAPI PciBusDriverBindingStart	(	IN EFI_DRIVER_BINDING_PROTOCOL *	This,
		IN EFI_HANDLE	Controller,
		IN EFI_DEVICE_PATH_PROTOCOL *	RemainingDevicePath
	)

Start this driver on ControllerHandle and enumerate Pci bus and start all device under PCI bus.

Parameters

This	Protocol instance pointer.
Controller	Handle of device to bind driver to.
RemainingDevicePath	Optional parameter use to pick a specific child device to start.

Return values

EFI_SUCCESS	This driver is added to ControllerHandle.
EFI_ALREADY_STARTED	This driver is already running on ControllerHandle.
other	This driver does not support this device.

Definition at line 232 of file PciBus.c.

◆ PciBusDriverBindingStop()

EFI_STATUS EFIAPI PciBusDriverBindingStop	(	IN EFI_DRIVER_BINDING_PROTOCOL *	This,
		IN EFI_HANDLE	Controller,
		IN UINTN	NumberOfChildren,
		IN EFI_HANDLE *	ChildHandleBuffer
	)

Stop this driver on ControllerHandle. Support stopping any child handles created by this driver.

Parameters

This	Protocol instance pointer.
Controller	Handle of device to stop driver on.
NumberOfChildren	Number of Handles in ChildHandleBuffer. If number of children is zero stop the entire bus driver.
ChildHandleBuffer	List of Child Handles to Stop.

Return values

EFI_SUCCESS	This driver is removed ControllerHandle.
other	This driver was not removed from this device.

Definition at line 402 of file PciBus.c.

◆ PciBusDriverBindingSupported()

EFI_STATUS EFIAPI PciBusDriverBindingSupported	(	IN EFI_DRIVER_BINDING_PROTOCOL *	This,
		IN EFI_HANDLE	Controller,
		IN EFI_DEVICE_PATH_PROTOCOL *	RemainingDevicePath
	)

Test to see if this driver supports ControllerHandle. Any ControllerHandle than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.

Parameters

This	Protocol instance pointer.
Controller	Handle of device to test.
RemainingDevicePath	Optional parameter use to pick a specific child device to start.

Return values

EFI_SUCCESS	This driver supports this device.
EFI_ALREADY_STARTED	This driver is already running on this device.
other	This driver does not support this device.

Definition at line 121 of file PciBus.c.

Variable Documentation

◆ gAllOne

UINT64 gAllOne

extern

Definition at line 34 of file PciBus.c.

◆ gAllZero

UINT64 gAllZero

extern

Definition at line 35 of file PciBus.c.

◆ gFullEnumeration

BOOLEAN gFullEnumeration

extern

Definition at line 33 of file PciBus.c.

◆ gIncompatiblePciDeviceSupport

EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL* gIncompatiblePciDeviceSupport

extern

Definition at line 31 of file PciBus.c.

◆ gPciBusComponentName

EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName

extern

Definition at line 14 of file ComponentName.c.

◆ gPciBusComponentName2

EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2

extern

Definition at line 23 of file ComponentName.c.

◆ gPciBusDriverBinding

EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding

extern

Definition at line 21 of file PciBus.c.

◆ gPciHostBridgeNumber

UINTN gPciHostBridgeNumber

extern

Definition at line 32 of file PciBus.c.

◆ gPciHostBrigeHandles

EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM]

extern

Definition at line 30 of file PciBus.c.

◆ gPciOverrideProtocol

EFI_PCI_OVERRIDE_PROTOCOL* gPciOverrideProtocol

extern

Definition at line 38 of file PciBus.c.

◆ gPciPlatformProtocol

EFI_PCI_PLATFORM_PROTOCOL* gPciPlatformProtocol

extern

Definition at line 37 of file PciBus.c.

◆ mReserveIsaAliases

BOOLEAN mReserveIsaAliases

extern

Definition at line 14 of file PciResourceSupport.c.

◆ mReserveVgaAliases

BOOLEAN mReserveVgaAliases

extern

Definition at line 15 of file PciResourceSupport.c.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ EFI_BRIDGE_IO16_DECODE_SUPPORTED

◆ EFI_BRIDGE_IO32_DECODE_SUPPORTED

◆ EFI_BRIDGE_MEM32_DECODE_SUPPORTED

◆ EFI_BRIDGE_MEM64_DECODE_SUPPORTED

◆ EFI_BRIDGE_PMEM32_DECODE_SUPPORTED

◆ EFI_BRIDGE_PMEM64_DECODE_SUPPORTED

◆ EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED

◆ EFI_PCI_BUS_OF_RID

◆ EFI_PCI_IOV_POLICY_ARI

◆ EFI_PCI_IOV_POLICY_MRIOV

◆ EFI_PCI_IOV_POLICY_SRIOV

◆ EFI_PCI_RID

◆ EFI_SET_ATTRIBUTES

◆ EFI_SET_SUPPORTS

◆ IS_PCI_GFX

◆ ISABASE

◆ ISALIMIT

◆ P2C_BAR_0

◆ P2C_IO_1

◆ P2C_IO_2

◆ P2C_MEM_1

◆ P2C_MEM_2

◆ PCI_CARD_BRIDGE_CONTROL

◆ PCI_CARD_IO_BASE_0_LOWER

◆ PCI_CARD_IO_BASE_0_UPPER

◆ PCI_CARD_IO_BASE_1_LOWER

◆ PCI_CARD_IO_BASE_1_UPPER

◆ PCI_CARD_IO_LIMIT_0_LOWER

◆ PCI_CARD_IO_LIMIT_0_UPPER

◆ PCI_CARD_IO_LIMIT_1_LOWER

◆ PCI_CARD_IO_LIMIT_1_UPPER

◆ PCI_CARD_MEMORY_BASE_0

◆ PCI_CARD_MEMORY_BASE_1

◆ PCI_CARD_MEMORY_LIMIT_0

◆ PCI_CARD_MEMORY_LIMIT_1

◆ PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE

◆ PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE

◆ PCI_IO_DEVICE_FROM_LINK

◆ PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS

◆ PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS

◆ PCI_IO_DEVICE_FROM_PCI_IO_THIS

◆ PCI_IO_DEVICE_SIGNATURE

◆ PCI_MAX_HOST_BRIDGE_NUM

◆ PPB_BAR_0

◆ PPB_BAR_1

◆ PPB_IO_RANGE

◆ PPB_MEM32_RANGE

◆ PPB_MEM64_RANGE

◆ PPB_PMEM32_RANGE

◆ PPB_PMEM64_RANGE

◆ RB_IO_RANGE

◆ RB_MEM32_RANGE

◆ RB_MEM64_RANGE

◆ RB_PMEM32_RANGE

◆ RB_PMEM64_RANGE

◆ VGABASE1

◆ VGABASE2

◆ VGALIMIT1

◆ VGALIMIT2

Typedef Documentation

◆ PCI_BAR

◆ PCI_IO_DEVICE

Enumeration Type Documentation

◆ PCI_BAR_TYPE

Function Documentation

◆ PciBusDriverBindingStart()

◆ PciBusDriverBindingStop()

◆ PciBusDriverBindingSupported()

Variable Documentation

◆ gAllOne

◆ gAllZero

◆ gFullEnumeration