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PciExpress21.h
Go to the documentation of this file.
1
10#ifndef _PCIEXPRESS21_H_
11#define _PCIEXPRESS21_H_
12
13#include <IndustryStandard/Pci30.h>
14
29#define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \
30 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
31
32#pragma pack(1)
36typedef union {
37 struct {
38 UINT16 Version : 4;
39 UINT16 DevicePortType : 4;
40 UINT16 SlotImplemented : 1;
41 UINT16 InterruptMessageNumber : 5;
42 UINT16 Undefined : 1;
43 UINT16 FlitModeSupported : 1;
44 } Bits;
45 UINT16 Uint16;
46} PCI_REG_PCIE_CAPABILITY;
47
48#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
49#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
50#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
51#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
52#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
53#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
54#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
55#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
56#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
57
58typedef union {
59 struct {
60 UINT32 MaxPayloadSize : 3;
61 UINT32 PhantomFunctions : 2;
62 UINT32 ExtendedTagField : 1;
63 UINT32 EndpointL0sAcceptableLatency : 3;
64 UINT32 EndpointL1AcceptableLatency : 3;
65 UINT32 Undefined : 3;
66 UINT32 RoleBasedErrorReporting : 1;
67 UINT32 ErrCorSubclassCapable : 1;
68 UINT32 RxMpsFixed : 1;
69 UINT32 CapturedSlotPowerLimitValue : 8;
70 UINT32 CapturedSlotPowerLimitScale : 2;
71 UINT32 FunctionLevelReset : 1;
72 UINT32 MixedMpsSupported : 1;
73 UINT32 Reserved2 : 2;
74 } Bits;
75 UINT32 Uint32;
76} PCI_REG_PCIE_DEVICE_CAPABILITY;
77
78typedef union {
79 struct {
80 UINT16 CorrectableError : 1;
81 UINT16 NonFatalError : 1;
82 UINT16 FatalError : 1;
83 UINT16 UnsupportedRequest : 1;
84 UINT16 RelaxedOrdering : 1;
85 UINT16 MaxPayloadSize : 3;
86 UINT16 ExtendedTagField : 1;
87 UINT16 PhantomFunctions : 1;
88 UINT16 AuxPower : 1;
89 UINT16 NoSnoop : 1;
90 UINT16 MaxReadRequestSize : 3;
91 UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
92 } Bits;
93 UINT16 Uint16;
94} PCI_REG_PCIE_DEVICE_CONTROL;
95
96#define PCIE_MAX_PAYLOAD_SIZE_128B 0
97#define PCIE_MAX_PAYLOAD_SIZE_256B 1
98#define PCIE_MAX_PAYLOAD_SIZE_512B 2
99#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
100#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
101#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
102#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
103#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
104
105#define PCIE_MAX_READ_REQ_SIZE_128B 0
106#define PCIE_MAX_READ_REQ_SIZE_256B 1
107#define PCIE_MAX_READ_REQ_SIZE_512B 2
108#define PCIE_MAX_READ_REQ_SIZE_1024B 3
109#define PCIE_MAX_READ_REQ_SIZE_2048B 4
110#define PCIE_MAX_READ_REQ_SIZE_4096B 5
111#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
112#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
113
114typedef union {
115 struct {
116 UINT16 CorrectableError : 1;
117 UINT16 NonFatalError : 1;
118 UINT16 FatalError : 1;
119 UINT16 UnsupportedRequest : 1;
120 UINT16 AuxPower : 1;
121 UINT16 TransactionsPending : 1;
122 UINT16 EmergencyPowerReductionDetected : 1;
123 UINT16 Reserved : 9;
124 } Bits;
125 UINT16 Uint16;
126} PCI_REG_PCIE_DEVICE_STATUS;
127
128typedef union {
129 struct {
130 UINT32 MaxLinkSpeed : 4;
131 UINT32 MaxLinkWidth : 6;
132 UINT32 Aspm : 2;
133 UINT32 L0sExitLatency : 3;
134 UINT32 L1ExitLatency : 3;
135 UINT32 ClockPowerManagement : 1;
136 UINT32 SurpriseDownError : 1;
137 UINT32 DataLinkLayerLinkActive : 1;
138 UINT32 LinkBandwidthNotification : 1;
139 UINT32 AspmOptionalityCompliance : 1;
140 UINT32 Reserved : 1;
141 UINT32 PortNumber : 8;
142 } Bits;
143 UINT32 Uint32;
144} PCI_REG_PCIE_LINK_CAPABILITY;
145
146#define PCIE_LINK_ASPM_L0S BIT0
147#define PCIE_LINK_ASPM_L1 BIT1
148
149typedef union {
150 struct {
151 UINT16 AspmControl : 2;
152 UINT16 PtmPropagationDelayB : 1;
153 UINT16 ReadCompletionBoundary : 1;
154 UINT16 LinkDisable : 1;
155 UINT16 RetrainLink : 1;
156 UINT16 CommonClockConfiguration : 1;
157 UINT16 ExtendedSynch : 1;
158 UINT16 ClockPowerManagement : 1;
159 UINT16 HardwareAutonomousWidthDisable : 1;
160 UINT16 LinkBandwidthManagementInterrupt : 1;
161 UINT16 LinkAutonomousBandwidthInterrupt : 1;
162 UINT16 SrisClocking : 1;
163 UINT16 FlitModeDisable : 1;
164 UINT16 DrsSignalingControl : 2;
165 } Bits;
166 UINT16 Uint16;
167} PCI_REG_PCIE_LINK_CONTROL;
168
169typedef union {
170 struct {
171 UINT16 CurrentLinkSpeed : 4;
172 UINT16 NegotiatedLinkWidth : 6;
173 UINT16 Undefined : 1;
174 UINT16 LinkTraining : 1;
175 UINT16 SlotClockConfiguration : 1;
176 UINT16 DataLinkLayerLinkActive : 1;
177 UINT16 LinkBandwidthManagement : 1;
178 UINT16 LinkAutonomousBandwidth : 1;
179 } Bits;
180 UINT16 Uint16;
181} PCI_REG_PCIE_LINK_STATUS;
182
183typedef union {
184 struct {
185 UINT32 AttentionButton : 1;
186 UINT32 PowerController : 1;
187 UINT32 MrlSensor : 1;
188 UINT32 AttentionIndicator : 1;
189 UINT32 PowerIndicator : 1;
190 UINT32 HotPlugSurprise : 1;
191 UINT32 HotPlugCapable : 1;
192 UINT32 SlotPowerLimitValue : 8;
193 UINT32 SlotPowerLimitScale : 2;
194 UINT32 ElectromechanicalInterlock : 1;
195 UINT32 NoCommandCompleted : 1;
196 UINT32 PhysicalSlotNumber : 13;
197 } Bits;
198 UINT32 Uint32;
199} PCI_REG_PCIE_SLOT_CAPABILITY;
200
201typedef union {
202 struct {
203 UINT16 AttentionButtonPressed : 1;
204 UINT16 PowerFaultDetected : 1;
205 UINT16 MrlSensorChanged : 1;
206 UINT16 PresenceDetectChanged : 1;
207 UINT16 CommandCompletedInterrupt : 1;
208 UINT16 HotPlugInterrupt : 1;
209 UINT16 AttentionIndicator : 2;
210 UINT16 PowerIndicator : 2;
211 UINT16 PowerController : 1;
212 UINT16 ElectromechanicalInterlock : 1;
213 UINT16 DataLinkLayerStateChanged : 1;
214 UINT16 AutoSlotPowerLimitDisable : 1;
215 UINT16 InbandPdDisable : 1;
216 UINT16 Reserved : 1;
217 } Bits;
218 UINT16 Uint16;
219} PCI_REG_PCIE_SLOT_CONTROL;
220
221typedef union {
222 struct {
223 UINT16 AttentionButtonPressed : 1;
224 UINT16 PowerFaultDetected : 1;
225 UINT16 MrlSensorChanged : 1;
226 UINT16 PresenceDetectChanged : 1;
227 UINT16 CommandCompleted : 1;
228 UINT16 MrlSensor : 1;
229 UINT16 PresenceDetect : 1;
230 UINT16 ElectromechanicalInterlock : 1;
231 UINT16 DataLinkLayerStateChanged : 1;
232 UINT16 Reserved : 7;
233 } Bits;
234 UINT16 Uint16;
235} PCI_REG_PCIE_SLOT_STATUS;
236
237typedef union {
238 struct {
239 UINT16 SystemErrorOnCorrectableError : 1;
240 UINT16 SystemErrorOnNonFatalError : 1;
241 UINT16 SystemErrorOnFatalError : 1;
242 UINT16 PmeInterrupt : 1;
243 UINT16 CrsSoftwareVisibility : 1;
244 UINT16 NoNfmSubtree : 1;
245 UINT16 Reserved : 10;
246 } Bits;
247 UINT16 Uint16;
248} PCI_REG_PCIE_ROOT_CONTROL;
249
250typedef union {
251 struct {
252 UINT16 CrsSoftwareVisibility : 1;
253 UINT16 Reserved : 15;
254 } Bits;
255 UINT16 Uint16;
256} PCI_REG_PCIE_ROOT_CAPABILITY;
257
258typedef union {
259 struct {
260 UINT32 PmeRequesterId : 16;
261 UINT32 PmeStatus : 1;
262 UINT32 PmePending : 1;
263 UINT32 Reserved : 14;
264 } Bits;
265 UINT32 Uint32;
266} PCI_REG_PCIE_ROOT_STATUS;
267
268typedef union {
269 struct {
270 UINT32 CompletionTimeoutRanges : 4;
271 UINT32 CompletionTimeoutDisable : 1;
272 UINT32 AriForwarding : 1;
273 UINT32 AtomicOpRouting : 1;
274 UINT32 AtomicOp32Completer : 1;
275 UINT32 AtomicOp64Completer : 1;
276 UINT32 Cas128Completer : 1;
277 UINT32 NoRoEnabledPrPrPassing : 1;
278 UINT32 LtrMechanism : 1;
279 UINT32 TphCompleter : 2;
280 UINT32 Reserved : 2;
281 UINT32 TenBitTagCompleterSupported : 1;
282 UINT32 TenBitTagRequesterSupported : 1;
283 UINT32 Obff : 2;
284 UINT32 ExtendedFmtField : 1;
285 UINT32 EndEndTlpPrefix : 1;
286 UINT32 MaxEndEndTlpPrefixes : 2;
287 UINT32 EmergencyPowerReductionSupported : 2;
288 UINT32 EmergencyPowerReductionInitializationRequired : 1;
289 UINT32 Reserved2 : 1;
290 UINT32 DmwrCompleter : 1;
291 UINT32 DmwrLengths : 2;
292 UINT32 FrsSupported : 1;
293 } Bits;
294 UINT32 Uint32;
295} PCI_REG_PCIE_DEVICE_CAPABILITY2;
296
297#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
298#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
299#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
300#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
301#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
302#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
303#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
304#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
305
306#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
307#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
308
309typedef union {
310 struct {
311 UINT16 CompletionTimeoutValue : 4;
312 UINT16 CompletionTimeoutDisable : 1;
313 UINT16 AriForwarding : 1;
314 UINT16 AtomicOpRequester : 1;
315 UINT16 AtomicOpEgressBlocking : 1;
316 UINT16 IdoRequest : 1;
317 UINT16 IdoCompletion : 1;
318 UINT16 LtrMechanism : 1;
319 UINT16 EmergencyPowerReductionRequest : 1;
320 UINT16 TenBitTagRequesterEnable : 1;
321 UINT16 Obff : 2;
322 UINT16 EndEndTlpPrefixBlocking : 1;
323 } Bits;
324 UINT16 Uint16;
325} PCI_REG_PCIE_DEVICE_CONTROL2;
326
327#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
328#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
329#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
330#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
331#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
332#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
333#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
334#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
335#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
336
337#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
338#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
339#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
340#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
341
342typedef union {
343 struct {
344 UINT32 Reserved : 1;
345 UINT32 LinkSpeedsVector : 7;
346 UINT32 Crosslink : 1;
347 UINT32 LowerSkpOsGeneration : 7;
348 UINT32 LowerSkpOsReception : 7;
349 UINT32 RetimerPresenceDetect : 1;
350 UINT32 TwoRetimersPresenceDetect : 1;
351 UINT32 Reserved2 : 6;
352 UINT32 DrsSupported : 1;
353 } Bits;
354 UINT32 Uint32;
355} PCI_REG_PCIE_LINK_CAPABILITY2;
356
357typedef union {
358 struct {
359 UINT16 TargetLinkSpeed : 4;
360 UINT16 EnterCompliance : 1;
361 UINT16 HardwareAutonomousSpeedDisable : 1;
362 UINT16 SelectableDeemphasis : 1;
363 UINT16 TransmitMargin : 3;
364 UINT16 EnterModifiedCompliance : 1;
365 UINT16 ComplianceSos : 1;
366 UINT16 CompliancePresetDeemphasis : 4;
367 } Bits;
368 UINT16 Uint16;
369} PCI_REG_PCIE_LINK_CONTROL2;
370
371typedef union {
372 struct {
373 UINT16 CurrentDeemphasisLevel : 1;
374 UINT16 EqualizationComplete : 1;
375 UINT16 EqualizationPhase1Successful : 1;
376 UINT16 EqualizationPhase2Successful : 1;
377 UINT16 EqualizationPhase3Successful : 1;
378 UINT16 LinkEqualizationRequest : 1;
379 UINT16 RetimerPresence : 1;
380 UINT16 TwoRetimersPresence : 1;
381 UINT16 CrosslinkResolution : 2;
382 UINT16 FlitModeStatus : 1;
383 UINT16 Reserved : 1;
384 UINT16 DownstreamComponentPresence : 3;
385 UINT16 DRSMessageReceived : 1;
386 } Bits;
387 UINT16 Uint16;
388} PCI_REG_PCIE_LINK_STATUS2;
389
390typedef union {
391 struct {
392 UINT32 InbandPdDisable : 1;
393 UINT32 Reserved : 30;
394 } Bits;
395 UINT32 Uint32;
396} PCI_REG_PCIE_SLOT_CAPABILITY2;
397
398typedef struct {
399 EFI_PCI_CAPABILITY_HDR Hdr;
400 PCI_REG_PCIE_CAPABILITY Capability;
401 PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
402 PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
403 PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
404 PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
405 PCI_REG_PCIE_LINK_CONTROL LinkControl;
406 PCI_REG_PCIE_LINK_STATUS LinkStatus;
407 PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
408 PCI_REG_PCIE_SLOT_CONTROL SlotControl;
409 PCI_REG_PCIE_SLOT_STATUS SlotStatus;
410 PCI_REG_PCIE_ROOT_CONTROL RootControl;
411 PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
412 PCI_REG_PCIE_ROOT_STATUS RootStatus;
413 PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
414 PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
415 UINT16 DeviceStatus2;
416 PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
417 PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
418 PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
419 PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
420 UINT16 SlotControl2;
421 UINT16 SlotStatus2;
422} PCI_CAPABILITY_PCIEXP;
423
424#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
425#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
426#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
427#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
428#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
429#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
430
431//
432// for SR-IOV
433//
434#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
435#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
436#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
437#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
438
439typedef struct {
440 UINT32 CapabilityHeader;
441 UINT32 Capability;
442 UINT16 Control;
443 UINT16 Status;
444 UINT16 InitialVFs;
445 UINT16 TotalVFs;
446 UINT16 NumVFs;
447 UINT8 FunctionDependencyLink;
448 UINT8 Reserved0;
449 UINT16 FirstVFOffset;
450 UINT16 VFStride;
451 UINT16 Reserved1;
452 UINT16 VFDeviceID;
453 UINT32 SupportedPageSize;
454 UINT32 SystemPageSize;
455 UINT32 VFBar[6];
456 UINT32 VFMigrationStateArrayOffset;
457} SR_IOV_CAPABILITY_REGISTER;
458
459#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
460#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
461#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
462#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
463#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
464#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
465#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
466#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
467#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
468#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
469#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
470#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
471#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
472#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
473#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
474#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
475#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
476#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
477#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
478
479typedef struct {
480 UINT32 CapabilityId : 16;
481 UINT32 CapabilityVersion : 4;
482 UINT32 NextCapabilityOffset : 12;
483} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;
484
485#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
486
487#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
488#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
489#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
490
491typedef union {
492 struct {
493 UINT32 Undefined : 1;
494 UINT32 Reserved : 3;
495 UINT32 DataLinkProtocolError : 1;
496 UINT32 SurpriseDownError : 1;
497 UINT32 Reserved2 : 6;
498 UINT32 PoisonedTlp : 1;
499 UINT32 FlowControlProtocolError : 1;
500 UINT32 CompletionTimeout : 1;
501 UINT32 CompleterAbort : 1;
502 UINT32 UnexpectedCompletion : 1;
503 UINT32 ReceiverOverflow : 1;
504 UINT32 MalformedTlp : 1;
505 UINT32 EcrcError : 1;
506 UINT32 UnsupportedRequestError : 1;
507 UINT32 AcsVoilation : 1;
508 UINT32 UncorrectableInternalError : 1;
509 UINT32 McBlockedTlp : 1;
510 UINT32 AtomicOpEgressBlocked : 1;
511 UINT32 TlpPrefixBlockedError : 1;
512 UINT32 Reserved3 : 6;
513 } Bits;
514 UINT32 Uint32;
515} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
516
517typedef struct {
518 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
519 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
520 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
521 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
522 UINT32 CorrectableErrorStatus;
523 UINT32 CorrectableErrorMask;
524 UINT32 AdvancedErrorCapabilitiesAndControl;
525 UINT32 HeaderLog[4];
526 UINT32 RootErrorCommand;
527 UINT32 RootErrorStatus;
528 UINT16 ErrorSourceIdentification;
529 UINT16 CorrectableErrorSourceIdentification;
530 UINT32 TlpPrefixLog[4];
531} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;
532
533#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
534#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
535#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
536
537typedef struct {
538 UINT32 VcResourceCapability : 24;
539 UINT32 PortArbTableOffset : 8;
540 UINT32 VcResourceControl;
541 UINT16 Reserved1;
542 UINT16 VcResourceStatus;
543} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;
544
545typedef struct {
546 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
547 UINT32 ExtendedVcCount : 3;
548 UINT32 PortVcCapability1 : 29;
549 UINT32 PortVcCapability2 : 24;
550 UINT32 VcArbTableOffset : 8;
551 UINT16 PortVcControl;
552 UINT16 PortVcStatus;
553 PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];
554} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;
555
556#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
557#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
558
559typedef struct {
560 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
561 UINT64 SerialNumber;
562} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;
563
564#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
565#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
566
567typedef struct {
568 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
569 UINT32 ElementSelfDescription;
570 UINT32 Reserved;
571 UINT32 LinkEntry[1];
572} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;
573
574#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
575
576#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
577#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
578
579typedef struct {
580 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
581 UINT32 RootComplexLinkCapabilities;
582 UINT16 RootComplexLinkControl;
583 UINT16 RootComplexLinkStatus;
584} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;
585
586#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
587#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
588
589typedef struct {
590 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
591 UINT32 DataSelect : 8;
592 UINT32 Reserved : 24;
593 UINT32 Data;
594 UINT32 PowerBudgetCapability : 1;
595 UINT32 Reserved2 : 7;
596 UINT32 Reserved3 : 24;
597} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;
598
599#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
600#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
601
602typedef struct {
603 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
604 UINT16 AcsCapability;
605 UINT16 AcsControl;
606 UINT8 EgressControlVectorArray[1];
607} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;
608
609#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
610#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
611
612#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
613#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
614
615typedef struct {
616 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
617 UINT32 AssociationBitmap;
618} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;
619
620#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
621#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
622
623typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;
624
625#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
626#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
627
628typedef struct {
629 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
630 UINT32 VendorSpecificHeader;
631 UINT8 VendorSpecific[1];
632} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;
633
634#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
635
636#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
637#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
638
639typedef struct {
640 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
641 UINT16 VendorId;
642 UINT16 DeviceId;
643 UINT32 RcrbCapabilities;
644 UINT32 RcrbControl;
645 UINT32 Reserved;
646} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;
647
648#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
649#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
650
651typedef struct {
652 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
653 UINT16 MultiCastCapability;
654 UINT16 MulticastControl;
655 UINT64 McBaseAddress;
656 UINT64 McReceiveAddress;
657 UINT64 McBlockAll;
658 UINT64 McBlockUntranslated;
659 UINT64 McOverlayBar;
660} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;
661
662#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
663#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
664
665typedef union {
666 struct {
667 UINT32 Reserved : 4;
668 UINT32 BarSizeCapability : 28;
669 } Bits;
670 UINT32 Uint32;
671} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;
672
673typedef union {
674 struct {
675 UINT32 BarIndex : 3;
676 UINT32 Reserved : 2;
677 UINT32 ResizableBarNumber : 3;
678 UINT32 BarSize : 6;
679 UINT32 Reserved2 : 2;
680 UINT32 BarSizeCapability : 16;
681 } Bits;
682 UINT32 Uint32;
683} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;
684
685typedef struct {
686 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;
687 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
688} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;
689
690typedef struct {
691 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
692 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];
693} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;
694
695#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)
696
697#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
698#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
699
700typedef struct {
701 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
702 UINT16 AriCapability;
703 UINT16 AriControl;
704} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;
705
706#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
707#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
708
709typedef struct {
710 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
711 UINT32 DpaCapability;
712 UINT32 DpaLatencyIndicator;
713 UINT16 DpaStatus;
714 UINT16 DpaControl;
715 UINT8 DpaPowerAllocationArray[1];
716} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;
717#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT32)(((POWER->DpaCapability)&0x0000000F))
718#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
719#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
720
721typedef struct {
722 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
723 UINT16 MaxSnoopLatency;
724 UINT16 MaxNoSnoopLatency;
725} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;
726
727#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
728#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
729
730typedef struct {
731 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
732 UINT32 TphRequesterCapability;
733 UINT32 TphRequesterControl;
734 UINT16 TphStTable[1];
735} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;
736
737#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
738
739#pragma pack()
740
741#endif
EFI_PCI_CAPABILITY_HDR
Definition: Pci22.h:655
PCI_CAPABILITY_PCIEXP
Definition: PciExpress21.h:398
PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
Definition: PciExpress21.h:602
PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
Definition: PciExpress21.h:517
PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
Definition: PciExpress21.h:700
PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
Definition: PciExpress21.h:709
PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
Definition: PciExpress21.h:615
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
Definition: PciExpress21.h:479
PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
Definition: PciExpress21.h:579
PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
Definition: PciExpress21.h:721
PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
Definition: PciExpress21.h:567
PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
Definition: PciExpress21.h:651
PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
Definition: PciExpress21.h:589
PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
Definition: PciExpress21.h:639
PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
Definition: PciExpress21.h:685
PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
Definition: PciExpress21.h:690
PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
Definition: PciExpress21.h:559
PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
Definition: PciExpress21.h:730
PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
Definition: PciExpress21.h:628
PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
Definition: PciExpress21.h:545
PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
Definition: PciExpress21.h:537
SR_IOV_CAPABILITY_REGISTER
Definition: PciExpress21.h:439
PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY
Definition: PciExpress21.h:665
PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL
Definition: PciExpress21.h:673
PCI_EXPRESS_REG_UNCORRECTABLE_ERROR
Definition: PciExpress21.h:491
PCI_REG_PCIE_CAPABILITY
Definition: PciExpress21.h:36
PCI_REG_PCIE_DEVICE_CAPABILITY2
Definition: PciExpress21.h:268
PCI_REG_PCIE_DEVICE_CAPABILITY
Definition: PciExpress21.h:58
PCI_REG_PCIE_DEVICE_CONTROL2
Definition: PciExpress21.h:309
PCI_REG_PCIE_DEVICE_CONTROL
Definition: PciExpress21.h:78
PCI_REG_PCIE_DEVICE_STATUS
Definition: PciExpress21.h:114
PCI_REG_PCIE_LINK_CAPABILITY2
Definition: PciExpress21.h:342
PCI_REG_PCIE_LINK_CAPABILITY
Definition: PciExpress21.h:128
PCI_REG_PCIE_LINK_CONTROL2
Definition: PciExpress21.h:357
PCI_REG_PCIE_LINK_CONTROL
Definition: PciExpress21.h:149
PCI_REG_PCIE_LINK_STATUS2
Definition: PciExpress21.h:371
PCI_REG_PCIE_LINK_STATUS
Definition: PciExpress21.h:169
PCI_REG_PCIE_ROOT_CAPABILITY
Definition: PciExpress21.h:250
PCI_REG_PCIE_ROOT_CONTROL
Definition: PciExpress21.h:237
PCI_REG_PCIE_ROOT_STATUS
Definition: PciExpress21.h:258
PCI_REG_PCIE_SLOT_CAPABILITY2
Definition: PciExpress21.h:390
PCI_REG_PCIE_SLOT_CAPABILITY
Definition: PciExpress21.h:183
PCI_REG_PCIE_SLOT_CONTROL
Definition: PciExpress21.h:201
PCI_REG_PCIE_SLOT_STATUS
Definition: PciExpress21.h:221