TianoCore EDK2 master
Loading...
Searching...
No Matches
PciExpress40.h File Reference

Go to the source code of this file.

Data Structures

union  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES
 
union  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL
 
union  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS
 
union  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL
 
struct  PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0
 
union  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
 
union  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
 
struct  PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC
 

Macros

#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID   0x0026
 
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1   0x1
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET   0x04
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET   0x08
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET   0x0C
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET   0x10
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET   0x14
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET   0x18
 
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET   0x20
 
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID   0x0023
 

Detailed Description

Support for the PCI Express 4.0 standard.

This header file may not define all structures. Please extend as required.

Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
Copyright (c) 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file PciExpress40.h.

Macro Definition Documentation

◆ PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID

#define PCI_EXPRESS_EXTENDED_CAPABILITY_DESIGNATED_VENDOR_SPECIFIC_ID   0x0023

The Designated Vendor Specific Capability definitions Based on section 7.9.6 of PCI Express Base Specification 4.0.

Definition at line 85 of file PciExpress40.h.

◆ PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID

#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID   0x0026

The Physical Layer PCI Express Extended Capability definitions.

Based on section 7.7.5 of PCI Express Base Specification 4.0.

Definition at line 23 of file PciExpress40.h.

◆ PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1

#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1   0x1

Definition at line 24 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET   0x04

Definition at line 27 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET   0x08

Definition at line 28 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET   0x14

Definition at line 31 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET   0x20

Definition at line 33 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET   0x10

Definition at line 30 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET   0x18

Definition at line 32 of file PciExpress40.h.

◆ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET

#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET   0x0C

Definition at line 29 of file PciExpress40.h.