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PciHostBridgeLib.h
Go to the documentation of this file.
1
10#ifndef __PCI_HOST_BRIDGE_LIB_H__
11#define __PCI_HOST_BRIDGE_LIB_H__
12
13//
14// (Base > Limit) indicates an aperture is not available.
15//
16typedef struct {
17 //
18 // Base and Limit are the device address instead of host address when
19 // Translation is not zero
20 //
21 UINT64 Base;
22 UINT64 Limit;
23 //
24 // According to UEFI 2.7, Device Address = Host Address + Translation,
25 // so Translation = Device Address - Host Address.
26 // On platforms where Translation is not zero, the subtraction is probably to
27 // be performed with UINT64 wrap-around semantics, for we may translate an
28 // above-4G host address into a below-4G device address for legacy PCIe device
29 // compatibility.
30 //
31 // NOTE: The alignment of Translation is required to be larger than any BAR
32 // alignment in the same root bridge, so that the same alignment can be
33 // applied to both device address and host address, which simplifies the
34 // situation and makes the current resource allocation code in generic PCI
35 // host bridge driver still work.
36 //
37 UINT64 Translation;
39
40typedef struct {
41 UINT32 Segment;
42 UINT64 Supports;
45 UINT64 Attributes;
48 BOOLEAN DmaAbove4G;
68
79EFIAPI
81 UINTN *Count
82 );
83
90VOID
91EFIAPI
93 PCI_ROOT_BRIDGE *Bridges,
94 UINTN Count
95 );
96
109VOID
110EFIAPI
112 EFI_HANDLE HostBridgeHandle,
113 VOID *Configuration
114 );
115
116#endif
UINT64 UINTN
PCI_ROOT_BRIDGE *EFIAPI PciHostBridgeGetRootBridges(UINTN *Count)
VOID EFIAPI PciHostBridgeFreeRootBridges(PCI_ROOT_BRIDGE *Bridges, UINTN Count)
VOID EFIAPI PciHostBridgeResourceConflict(EFI_HANDLE HostBridgeHandle, VOID *Configuration)
VOID * EFI_HANDLE
Definition: UefiBaseType.h:33
PCI_ROOT_BRIDGE_APERTURE Io
IO aperture which can be used by the root bridge.
BOOLEAN ResourceAssigned
PCI_ROOT_BRIDGE_APERTURE PMem
Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
BOOLEAN NoExtendedConfigSpace
UINT32 Segment
Segment number.
EFI_DEVICE_PATH_PROTOCOL * DevicePath
Device path.
PCI_ROOT_BRIDGE_APERTURE Mem
MMIO aperture below 4GB which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE PMemAbove4G
Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE MemAbove4G
MMIO aperture above 4GB which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE Bus
Bus aperture which can be used by the root bridge.
UINT64 AllocationAttributes