9#ifndef PLATFORM_INIT_LIB_H_
10#define PLATFORM_INIT_LIB_H_
17 UINT16 HostBridgeDevId;
19 UINT64 PcdConfidentialComputingGuestAttr;
25 BOOLEAN SmmSmramRequire;
26 BOOLEAN Q35SmramAtDefaultSmbase;
30 UINT64 FirstNonAddress;
31 UINT8 PhysMemAddressWidth;
35 BOOLEAN PcdSetNxForStack;
36 UINT64 PcdTdxSharedBitMask;
38 UINT64 PcdPciMmio64Base;
39 UINT64 PcdPciMmio64Size;
40 UINT32 PcdPciMmio32Base;
41 UINT32 PcdPciMmio32Size;
45 UINT64 PcdEmuVariableNvStoreReserved;
46 UINT32 PcdCpuBootLogicalProcessorNumber;
47 UINT32 PcdCpuMaxLogicalProcessorNumber;
48 UINT32 DefaultMaxCpuNumber;
50 UINT32 S3AcpiReservedMemoryBase;
51 UINT32 S3AcpiReservedMemorySize;
53 UINT64 FeatureControlValue;
55 BOOLEAN QemuFwCfgChecked;
56 BOOLEAN QemuFwCfgSupported;
57 BOOLEAN QemuFwCfgDmaSupported;
108PlatformAddIoMemoryBaseSizeHob (
115PlatformAddIoMemoryRangeHob (
122PlatformAddMemoryBaseSizeHob (
129PlatformAddMemoryRangeHob (
136PlatformAddReservedMemoryBaseSizeHob (
138 IN UINT64 MemorySize,
144PlatformQemuUc32BaseInitialization (
150PlatformGetSystemMemorySizeBelow4gb (
175PlatformQemuInitializeRamForS3 (
181PlatformMemMapInitialization (
199PlatformMiscInitialization (
240 IN UINT8 *NvVarStoreBase,
241 IN UINT32 NvVarStoreSize
275 IN VOID *EmuVariableNvStore
BOOLEAN SevEsIsEnabled(VOID)
UINT64 EFI_PHYSICAL_ADDRESS