#include <Library/PciLib.h>
#include <Uefi/UefiBaseType.h>
#include <Uefi/UefiSpec.h>
#include <Protocol/PciRootBridgeIo.h>

Macros
#define	INTEL_Q35_MCH_DEVICE_ID 0x29C0

#define	DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))

#define	MCH_EXT_TSEG_MB 0x50

#define	MCH_EXT_TSEG_MB_QUERY 0xFFFF

#define	MCH_GGC 0x52

#define	MCH_GGC_IVD BIT1

#define	MCH_PCIEXBAR_LOW 0x60

#define	MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF

#define	MCH_PCIEXBAR_BUS_FF 0

#define	MCH_PCIEXBAR_EN BIT0

#define	MCH_PCIEXBAR_HIGH 0x64

#define	MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0

#define	MCH_PAM0 0x90

#define	MCH_PAM1 0x91

#define	MCH_PAM2 0x92

#define	MCH_PAM3 0x93

#define	MCH_PAM4 0x94

#define	MCH_PAM5 0x95

#define	MCH_PAM6 0x96

#define	MCH_DEFAULT_SMBASE_CTL 0x9C

#define	MCH_DEFAULT_SMBASE_QUERY 0xFF

#define	MCH_DEFAULT_SMBASE_IN_RAM 0x01

#define	MCH_DEFAULT_SMBASE_LCK 0x02

#define	MCH_DEFAULT_SMBASE_SIZE SIZE_128KB

#define	MCH_SMRAM 0x9D

#define	MCH_SMRAM_D_LCK BIT4

#define	MCH_SMRAM_G_SMRAME BIT3

#define	MCH_ESMRAMC 0x9E

#define	MCH_ESMRAMC_H_SMRAME BIT7

#define	MCH_ESMRAMC_E_SMERR BIT6

#define	MCH_ESMRAMC_SM_CACHE BIT5

#define	MCH_ESMRAMC_SM_L1 BIT4

#define	MCH_ESMRAMC_SM_L2 BIT3

#define	MCH_ESMRAMC_TSEG_EXT (BIT2 \| BIT1)

#define	MCH_ESMRAMC_TSEG_8MB BIT2

#define	MCH_ESMRAMC_TSEG_2MB BIT1

#define	MCH_ESMRAMC_TSEG_1MB 0

#define	MCH_ESMRAMC_TSEG_MASK (BIT2 \| BIT1)

#define	MCH_ESMRAMC_T_EN BIT0

#define	MCH_GBSM 0xA4

#define	MCH_GBSM_MB_SHIFT 20

#define	MCH_BGSM 0xA8

#define	MCH_BGSM_MB_SHIFT 20

#define	MCH_TSEGMB 0xAC

#define	MCH_TSEGMB_MB_SHIFT 20

#define	MCH_TOLUD 0xB0

#define	MCH_TOLUD_MB_SHIFT 4

#define	POWER_MGMT_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))

#define	POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))

#define	ICH9_PMBASE 0x40

#define	ICH9_PMBASE_MASK

#define	ICH9_ACPI_CNTL 0x44

#define	ICH9_ACPI_CNTL_ACPI_EN BIT7

#define	ICH9_GEN_PMCON_1 0xA0

#define	ICH9_GEN_PMCON_1_SMI_LOCK BIT4

#define	ICH9_RCBA 0xF0

#define	ICH9_RCBA_EN BIT0

#define	ICH9_APM_CNT 0xB2

#define	ICH9_APM_CNT_CPU_HOTPLUG 0x04

#define	ICH9_APM_STS 0xB3

#define	ICH9_CPU_HOTPLUG_BASE 0x0CD8

#define	ICH9_PMBASE_OFS_SMI_EN 0x30

#define	ICH9_SMI_EN_APMC_EN BIT5

#define	ICH9_SMI_EN_GBL_SMI_EN BIT0

#define	ICH9_ROOT_COMPLEX_BASE 0xFED1C000

Detailed Description

Various register numbers and value bits based on the following publications:

Intel(R) datasheet 316966-002
Intel(R) datasheet 316972-004

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file Q35MchIch9.h.

Macro Definition Documentation

◆ DRAMC_REGISTER_Q35

#define DRAMC_REGISTER_Q35 ( Offset ) PCI_LIB_ADDRESS (0, 0, 0, (Offset))

Definition at line 28 of file Q35MchIch9.h.

◆ ICH9_ACPI_CNTL

#define ICH9_ACPI_CNTL 0x44

Definition at line 100 of file Q35MchIch9.h.

◆ ICH9_ACPI_CNTL_ACPI_EN

#define ICH9_ACPI_CNTL_ACPI_EN BIT7

Definition at line 101 of file Q35MchIch9.h.

◆ ICH9_APM_CNT

#define ICH9_APM_CNT 0xB2

Definition at line 112 of file Q35MchIch9.h.

◆ ICH9_APM_CNT_CPU_HOTPLUG

#define ICH9_APM_CNT_CPU_HOTPLUG 0x04

Definition at line 113 of file Q35MchIch9.h.

◆ ICH9_APM_STS

#define ICH9_APM_STS 0xB3

Definition at line 114 of file Q35MchIch9.h.

◆ ICH9_CPU_HOTPLUG_BASE

#define ICH9_CPU_HOTPLUG_BASE 0x0CD8

Definition at line 116 of file Q35MchIch9.h.

◆ ICH9_GEN_PMCON_1

#define ICH9_GEN_PMCON_1 0xA0

Definition at line 103 of file Q35MchIch9.h.

◆ ICH9_GEN_PMCON_1_SMI_LOCK

#define ICH9_GEN_PMCON_1_SMI_LOCK BIT4

Definition at line 104 of file Q35MchIch9.h.

◆ ICH9_PMBASE

#define ICH9_PMBASE 0x40

Definition at line 96 of file Q35MchIch9.h.

◆ ICH9_PMBASE_MASK

#define ICH9_PMBASE_MASK

Value:

(BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \

BIT10 | BIT9 | BIT8 | BIT7)

Definition at line 97 of file Q35MchIch9.h.

◆ ICH9_PMBASE_OFS_SMI_EN

#define ICH9_PMBASE_OFS_SMI_EN 0x30

Definition at line 121 of file Q35MchIch9.h.

◆ ICH9_RCBA

#define ICH9_RCBA 0xF0

Definition at line 106 of file Q35MchIch9.h.

◆ ICH9_RCBA_EN

#define ICH9_RCBA_EN BIT0

Definition at line 107 of file Q35MchIch9.h.

◆ ICH9_ROOT_COMPLEX_BASE

#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000

Definition at line 125 of file Q35MchIch9.h.

◆ ICH9_SMI_EN_APMC_EN

#define ICH9_SMI_EN_APMC_EN BIT5

Definition at line 122 of file Q35MchIch9.h.

◆ ICH9_SMI_EN_GBL_SMI_EN

#define ICH9_SMI_EN_GBL_SMI_EN BIT0

Definition at line 123 of file Q35MchIch9.h.

◆ INTEL_Q35_MCH_DEVICE_ID

#define INTEL_Q35_MCH_DEVICE_ID 0x29C0

Definition at line 23 of file Q35MchIch9.h.

◆ MCH_BGSM

#define MCH_BGSM 0xA8

Definition at line 78 of file Q35MchIch9.h.

◆ MCH_BGSM_MB_SHIFT

#define MCH_BGSM_MB_SHIFT 20

Definition at line 79 of file Q35MchIch9.h.

◆ MCH_DEFAULT_SMBASE_CTL

#define MCH_DEFAULT_SMBASE_CTL 0x9C

Definition at line 52 of file Q35MchIch9.h.

◆ MCH_DEFAULT_SMBASE_IN_RAM

#define MCH_DEFAULT_SMBASE_IN_RAM 0x01

Definition at line 54 of file Q35MchIch9.h.

◆ MCH_DEFAULT_SMBASE_LCK

#define MCH_DEFAULT_SMBASE_LCK 0x02

Definition at line 55 of file Q35MchIch9.h.

◆ MCH_DEFAULT_SMBASE_QUERY

#define MCH_DEFAULT_SMBASE_QUERY 0xFF

Definition at line 53 of file Q35MchIch9.h.

◆ MCH_DEFAULT_SMBASE_SIZE

#define MCH_DEFAULT_SMBASE_SIZE SIZE_128KB

Definition at line 56 of file Q35MchIch9.h.

◆ MCH_ESMRAMC

#define MCH_ESMRAMC 0x9E

Definition at line 62 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_E_SMERR

#define MCH_ESMRAMC_E_SMERR BIT6

Definition at line 64 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_H_SMRAME

#define MCH_ESMRAMC_H_SMRAME BIT7

Definition at line 63 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_SM_CACHE

#define MCH_ESMRAMC_SM_CACHE BIT5

Definition at line 65 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_SM_L1

#define MCH_ESMRAMC_SM_L1 BIT4

Definition at line 66 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_SM_L2

#define MCH_ESMRAMC_SM_L2 BIT3

Definition at line 67 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_T_EN

#define MCH_ESMRAMC_T_EN BIT0

Definition at line 73 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_TSEG_1MB

#define MCH_ESMRAMC_TSEG_1MB 0

Definition at line 71 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_TSEG_2MB

#define MCH_ESMRAMC_TSEG_2MB BIT1

Definition at line 70 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_TSEG_8MB

#define MCH_ESMRAMC_TSEG_8MB BIT2

Definition at line 69 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_TSEG_EXT

#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)

Definition at line 68 of file Q35MchIch9.h.

◆ MCH_ESMRAMC_TSEG_MASK

#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)

Definition at line 72 of file Q35MchIch9.h.

◆ MCH_EXT_TSEG_MB

#define MCH_EXT_TSEG_MB 0x50

Definition at line 30 of file Q35MchIch9.h.

◆ MCH_EXT_TSEG_MB_QUERY

#define MCH_EXT_TSEG_MB_QUERY 0xFFFF

Definition at line 31 of file Q35MchIch9.h.

◆ MCH_GBSM

#define MCH_GBSM 0xA4

Definition at line 75 of file Q35MchIch9.h.

◆ MCH_GBSM_MB_SHIFT

#define MCH_GBSM_MB_SHIFT 20

Definition at line 76 of file Q35MchIch9.h.

◆ MCH_GGC

#define MCH_GGC 0x52

Definition at line 33 of file Q35MchIch9.h.

◆ MCH_GGC_IVD

#define MCH_GGC_IVD BIT1

Definition at line 34 of file Q35MchIch9.h.

◆ MCH_PAM0

#define MCH_PAM0 0x90

Definition at line 44 of file Q35MchIch9.h.

◆ MCH_PAM1

#define MCH_PAM1 0x91

Definition at line 45 of file Q35MchIch9.h.

◆ MCH_PAM2

#define MCH_PAM2 0x92

Definition at line 46 of file Q35MchIch9.h.

◆ MCH_PAM3

#define MCH_PAM3 0x93

Definition at line 47 of file Q35MchIch9.h.

◆ MCH_PAM4

#define MCH_PAM4 0x94

Definition at line 48 of file Q35MchIch9.h.

◆ MCH_PAM5

#define MCH_PAM5 0x95

Definition at line 49 of file Q35MchIch9.h.

◆ MCH_PAM6

#define MCH_PAM6 0x96

Definition at line 50 of file Q35MchIch9.h.

◆ MCH_PCIEXBAR_BUS_FF

#define MCH_PCIEXBAR_BUS_FF 0

Definition at line 38 of file Q35MchIch9.h.

◆ MCH_PCIEXBAR_EN

#define MCH_PCIEXBAR_EN BIT0

Definition at line 39 of file Q35MchIch9.h.

◆ MCH_PCIEXBAR_HIGH

#define MCH_PCIEXBAR_HIGH 0x64

Definition at line 41 of file Q35MchIch9.h.

◆ MCH_PCIEXBAR_HIGHMASK

#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0

Definition at line 42 of file Q35MchIch9.h.

◆ MCH_PCIEXBAR_LOW

#define MCH_PCIEXBAR_LOW 0x60

Definition at line 36 of file Q35MchIch9.h.

◆ MCH_PCIEXBAR_LOWMASK

#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF

Definition at line 37 of file Q35MchIch9.h.

◆ MCH_SMRAM

#define MCH_SMRAM 0x9D

Definition at line 58 of file Q35MchIch9.h.

◆ MCH_SMRAM_D_LCK

#define MCH_SMRAM_D_LCK BIT4

Definition at line 59 of file Q35MchIch9.h.

◆ MCH_SMRAM_G_SMRAME

#define MCH_SMRAM_G_SMRAME BIT3

Definition at line 60 of file Q35MchIch9.h.

◆ MCH_TOLUD

#define MCH_TOLUD 0xB0

Definition at line 84 of file Q35MchIch9.h.

◆ MCH_TOLUD_MB_SHIFT

#define MCH_TOLUD_MB_SHIFT 4

Definition at line 85 of file Q35MchIch9.h.

◆ MCH_TSEGMB

#define MCH_TSEGMB 0xAC

Definition at line 81 of file Q35MchIch9.h.

◆ MCH_TSEGMB_MB_SHIFT

#define MCH_TSEGMB_MB_SHIFT 20

Definition at line 82 of file Q35MchIch9.h.

◆ POWER_MGMT_REGISTER_Q35

#define POWER_MGMT_REGISTER_Q35 ( Offset ) PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))

Definition at line 90 of file Q35MchIch9.h.

◆ POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS

#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS ( Offset ) EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))

Definition at line 93 of file Q35MchIch9.h.

Macros