TianoCore EDK2 master
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RiscVEncoding.h
Go to the documentation of this file.
1
10#ifndef RISCV_ENCODING_H_
11#define RISCV_ENCODING_H_
12
13#define MSTATUS_SIE 0x00000002UL
14#define MSTATUS_MIE 0x00000008UL
15#define MSTATUS_SPIE_SHIFT 5
16#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT)
17#define MSTATUS_UBE 0x00000040UL
18#define MSTATUS_MPIE 0x00000080UL
19#define MSTATUS_SPP_SHIFT 8
20#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
21#define MSTATUS_MPP_SHIFT 11
22#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
23#define MSTATUS_FS 0x00006000UL
24
25#define SSTATUS_SIE MSTATUS_SIE
26#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT
27#define SSTATUS_SPIE MSTATUS_SPIE
28#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT
29#define SSTATUS_SPP MSTATUS_SPP
30
31#define IRQ_S_SOFT 1
32#define IRQ_VS_SOFT 2
33#define IRQ_M_SOFT 3
34#define IRQ_S_TIMER 5
35#define IRQ_VS_TIMER 6
36#define IRQ_M_TIMER 7
37#define IRQ_S_EXT 9
38#define IRQ_VS_EXT 10
39#define IRQ_M_EXT 11
40#define IRQ_S_GEXT 12
41#define IRQ_PMU_OVF 13
42
43#define MIP_SSIP (1UL << IRQ_S_SOFT)
44#define MIP_VSSIP (1UL << IRQ_VS_SOFT)
45#define MIP_MSIP (1UL << IRQ_M_SOFT)
46#define MIP_STIP (1UL << IRQ_S_TIMER)
47#define MIP_VSTIP (1UL << IRQ_VS_TIMER)
48#define MIP_MTIP (1UL << IRQ_M_TIMER)
49#define MIP_SEIP (1UL << IRQ_S_EXT)
50#define MIP_VSEIP (1UL << IRQ_VS_EXT)
51#define MIP_MEIP (1UL << IRQ_M_EXT)
52#define MIP_SGEIP (1UL << IRQ_S_GEXT)
53#define MIP_LCOFIP (1UL << IRQ_PMU_OVF)
54
55#define SIP_SSIP MIP_SSIP
56#define SIP_STIP MIP_STIP
57
58#define PRV_U 0UL
59#define PRV_S 1UL
60#define PRV_M 3UL
61
62#define SATP64_MODE 0xF000000000000000ULL
63#define SATP64_MODE_SHIFT 60
64#define SATP64_ASID 0x0FFFF00000000000ULL
65#define SATP64_PPN 0x00000FFFFFFFFFFFULL
66
67#define SATP_MODE_OFF 0UL
68#define SATP_MODE_SV32 1UL
69#define SATP_MODE_SV39 8UL
70#define SATP_MODE_SV48 9UL
71#define SATP_MODE_SV57 10UL
72#define SATP_MODE_SV64 11UL
73
74#define SATP_MODE SATP64_MODE
75
76/* User Counters/Timers */
77#define CSR_CYCLE 0xc00
78#define CSR_TIME 0xc01
79
80/* Floating-Point */
81#define CSR_FCSR 0x003
82
83/* Supervisor Trap Setup */
84#define CSR_SSTATUS 0x100
85#define CSR_SEDELEG 0x102
86#define CSR_SIDELEG 0x103
87#define CSR_SIE 0x104
88#define CSR_STVEC 0x105
89
90/* Supervisor Configuration */
91#define CSR_SENVCFG 0x10a
92
93/* Supervisor Trap Handling */
94#define CSR_SSCRATCH 0x140
95#define CSR_SEPC 0x141
96#define CSR_SCAUSE 0x142
97#define CSR_STVAL 0x143
98#define CSR_SIP 0x144
99
100/* Supervisor Protection and Translation */
101#define CSR_SATP 0x180
102
103/* Sstc extension */
104#define CSR_STIMECMP 0x14D
105
106/* Trap/Exception Causes */
107#define CAUSE_MISALIGNED_FETCH 0x0
108#define CAUSE_FETCH_ACCESS 0x1
109#define CAUSE_ILLEGAL_INSTRUCTION 0x2
110#define CAUSE_BREAKPOINT 0x3
111#define CAUSE_MISALIGNED_LOAD 0x4
112#define CAUSE_LOAD_ACCESS 0x5
113#define CAUSE_MISALIGNED_STORE 0x6
114#define CAUSE_STORE_ACCESS 0x7
115#define CAUSE_USER_ECALL 0x8
116#define CAUSE_SUPERVISOR_ECALL 0x9
117#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa
118#define CAUSE_MACHINE_ECALL 0xb
119#define CAUSE_FETCH_PAGE_FAULT 0xc
120#define CAUSE_LOAD_PAGE_FAULT 0xd
121#define CAUSE_STORE_PAGE_FAULT 0xf
122#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
123#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
124#define CAUSE_VIRTUAL_INST_FAULT 0x16
125#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
126
127/* Sstc extension */
128#define CSR_SEED 0x15
129
130#define SEED_OPST_MASK 0xc0000000
131#define SEED_OPST_BIST 0x00000000
132#define SEED_OPST_WAIT 0x40000000
133#define SEED_OPST_ES16 0x80000000
134#define SEED_OPST_DEAD 0xc0000000
135#define SEED_ENTROPY_MASK 0xffff
136
137#endif