TianoCore EDK2 master
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Macros | |
#define | MSTATUS_SIE 0x00000002UL |
#define | MSTATUS_MIE 0x00000008UL |
#define | MSTATUS_SPIE_SHIFT 5 |
#define | MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) |
#define | MSTATUS_UBE 0x00000040UL |
#define | MSTATUS_MPIE 0x00000080UL |
#define | MSTATUS_SPP_SHIFT 8 |
#define | MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) |
#define | MSTATUS_MPP_SHIFT 11 |
#define | MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) |
#define | MSTATUS_FS 0x00006000UL |
#define | SSTATUS_SIE MSTATUS_SIE |
#define | SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT |
#define | SSTATUS_SPIE MSTATUS_SPIE |
#define | SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT |
#define | SSTATUS_SPP MSTATUS_SPP |
#define | IRQ_S_SOFT 1 |
#define | IRQ_VS_SOFT 2 |
#define | IRQ_M_SOFT 3 |
#define | IRQ_S_TIMER 5 |
#define | IRQ_VS_TIMER 6 |
#define | IRQ_M_TIMER 7 |
#define | IRQ_S_EXT 9 |
#define | IRQ_VS_EXT 10 |
#define | IRQ_M_EXT 11 |
#define | IRQ_S_GEXT 12 |
#define | IRQ_PMU_OVF 13 |
#define | MIP_SSIP (1UL << IRQ_S_SOFT) |
#define | MIP_VSSIP (1UL << IRQ_VS_SOFT) |
#define | MIP_MSIP (1UL << IRQ_M_SOFT) |
#define | MIP_STIP (1UL << IRQ_S_TIMER) |
#define | MIP_VSTIP (1UL << IRQ_VS_TIMER) |
#define | MIP_MTIP (1UL << IRQ_M_TIMER) |
#define | MIP_SEIP (1UL << IRQ_S_EXT) |
#define | MIP_VSEIP (1UL << IRQ_VS_EXT) |
#define | MIP_MEIP (1UL << IRQ_M_EXT) |
#define | MIP_SGEIP (1UL << IRQ_S_GEXT) |
#define | MIP_LCOFIP (1UL << IRQ_PMU_OVF) |
#define | SIP_SSIP MIP_SSIP |
#define | SIP_STIP MIP_STIP |
#define | PRV_U 0UL |
#define | PRV_S 1UL |
#define | PRV_M 3UL |
#define | SATP64_MODE 0xF000000000000000ULL |
#define | SATP64_MODE_SHIFT 60 |
#define | SATP64_ASID 0x0FFFF00000000000ULL |
#define | SATP64_PPN 0x00000FFFFFFFFFFFULL |
#define | SATP_MODE_OFF 0UL |
#define | SATP_MODE_SV32 1UL |
#define | SATP_MODE_SV39 8UL |
#define | SATP_MODE_SV48 9UL |
#define | SATP_MODE_SV57 10UL |
#define | SATP_MODE_SV64 11UL |
#define | SATP_MODE SATP64_MODE |
#define | CSR_CYCLE 0xc00 |
#define | CSR_TIME 0xc01 |
#define | CSR_FCSR 0x003 |
#define | CSR_SSTATUS 0x100 |
#define | CSR_SEDELEG 0x102 |
#define | CSR_SIDELEG 0x103 |
#define | CSR_SIE 0x104 |
#define | CSR_STVEC 0x105 |
#define | CSR_SENVCFG 0x10a |
#define | CSR_SSCRATCH 0x140 |
#define | CSR_SEPC 0x141 |
#define | CSR_SCAUSE 0x142 |
#define | CSR_STVAL 0x143 |
#define | CSR_SIP 0x144 |
#define | CSR_SATP 0x180 |
#define | CSR_STIMECMP 0x14D |
#define | CAUSE_MISALIGNED_FETCH 0x0 |
#define | CAUSE_FETCH_ACCESS 0x1 |
#define | CAUSE_ILLEGAL_INSTRUCTION 0x2 |
#define | CAUSE_BREAKPOINT 0x3 |
#define | CAUSE_MISALIGNED_LOAD 0x4 |
#define | CAUSE_LOAD_ACCESS 0x5 |
#define | CAUSE_MISALIGNED_STORE 0x6 |
#define | CAUSE_STORE_ACCESS 0x7 |
#define | CAUSE_USER_ECALL 0x8 |
#define | CAUSE_SUPERVISOR_ECALL 0x9 |
#define | CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa |
#define | CAUSE_MACHINE_ECALL 0xb |
#define | CAUSE_FETCH_PAGE_FAULT 0xc |
#define | CAUSE_LOAD_PAGE_FAULT 0xd |
#define | CAUSE_STORE_PAGE_FAULT 0xf |
#define | CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 |
#define | CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 |
#define | CAUSE_VIRTUAL_INST_FAULT 0x16 |
#define | CAUSE_STORE_GUEST_PAGE_FAULT 0x17 |
#define | CSR_SEED 0x15 |
#define | SEED_OPST_MASK 0xc0000000 |
#define | SEED_OPST_BIST 0x00000000 |
#define | SEED_OPST_WAIT 0x40000000 |
#define | SEED_OPST_ES16 0x80000000 |
#define | SEED_OPST_DEAD 0xc0000000 |
#define | SEED_ENTROPY_MASK 0xffff |
RISC-V CSR encodings
Copyright (c) 2019, Western Digital Corporation or its affiliates. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
Definition in file RiscVEncoding.h.
#define CAUSE_BREAKPOINT 0x3 |
Definition at line 110 of file RiscVEncoding.h.
#define CAUSE_FETCH_ACCESS 0x1 |
Definition at line 108 of file RiscVEncoding.h.
#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 |
Definition at line 122 of file RiscVEncoding.h.
#define CAUSE_FETCH_PAGE_FAULT 0xc |
Definition at line 119 of file RiscVEncoding.h.
#define CAUSE_ILLEGAL_INSTRUCTION 0x2 |
Definition at line 109 of file RiscVEncoding.h.
#define CAUSE_LOAD_ACCESS 0x5 |
Definition at line 112 of file RiscVEncoding.h.
#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 |
Definition at line 123 of file RiscVEncoding.h.
#define CAUSE_LOAD_PAGE_FAULT 0xd |
Definition at line 120 of file RiscVEncoding.h.
#define CAUSE_MACHINE_ECALL 0xb |
Definition at line 118 of file RiscVEncoding.h.
#define CAUSE_MISALIGNED_FETCH 0x0 |
Definition at line 107 of file RiscVEncoding.h.
#define CAUSE_MISALIGNED_LOAD 0x4 |
Definition at line 111 of file RiscVEncoding.h.
#define CAUSE_MISALIGNED_STORE 0x6 |
Definition at line 113 of file RiscVEncoding.h.
#define CAUSE_STORE_ACCESS 0x7 |
Definition at line 114 of file RiscVEncoding.h.
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 |
Definition at line 125 of file RiscVEncoding.h.
#define CAUSE_STORE_PAGE_FAULT 0xf |
Definition at line 121 of file RiscVEncoding.h.
#define CAUSE_SUPERVISOR_ECALL 0x9 |
Definition at line 116 of file RiscVEncoding.h.
#define CAUSE_USER_ECALL 0x8 |
Definition at line 115 of file RiscVEncoding.h.
#define CAUSE_VIRTUAL_INST_FAULT 0x16 |
Definition at line 124 of file RiscVEncoding.h.
#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa |
Definition at line 117 of file RiscVEncoding.h.
#define CSR_CYCLE 0xc00 |
Definition at line 77 of file RiscVEncoding.h.
#define CSR_FCSR 0x003 |
Definition at line 81 of file RiscVEncoding.h.
#define CSR_SATP 0x180 |
Definition at line 101 of file RiscVEncoding.h.
#define CSR_SCAUSE 0x142 |
Definition at line 96 of file RiscVEncoding.h.
#define CSR_SEDELEG 0x102 |
Definition at line 85 of file RiscVEncoding.h.
#define CSR_SEED 0x15 |
Definition at line 128 of file RiscVEncoding.h.
#define CSR_SENVCFG 0x10a |
Definition at line 91 of file RiscVEncoding.h.
#define CSR_SEPC 0x141 |
Definition at line 95 of file RiscVEncoding.h.
#define CSR_SIDELEG 0x103 |
Definition at line 86 of file RiscVEncoding.h.
#define CSR_SIE 0x104 |
Definition at line 87 of file RiscVEncoding.h.
#define CSR_SIP 0x144 |
Definition at line 98 of file RiscVEncoding.h.
#define CSR_SSCRATCH 0x140 |
Definition at line 94 of file RiscVEncoding.h.
#define CSR_SSTATUS 0x100 |
Definition at line 84 of file RiscVEncoding.h.
#define CSR_STIMECMP 0x14D |
Definition at line 104 of file RiscVEncoding.h.
#define CSR_STVAL 0x143 |
Definition at line 97 of file RiscVEncoding.h.
#define CSR_STVEC 0x105 |
Definition at line 88 of file RiscVEncoding.h.
#define CSR_TIME 0xc01 |
Definition at line 78 of file RiscVEncoding.h.
#define IRQ_M_EXT 11 |
Definition at line 39 of file RiscVEncoding.h.
#define IRQ_M_SOFT 3 |
Definition at line 33 of file RiscVEncoding.h.
#define IRQ_M_TIMER 7 |
Definition at line 36 of file RiscVEncoding.h.
#define IRQ_PMU_OVF 13 |
Definition at line 41 of file RiscVEncoding.h.
#define IRQ_S_EXT 9 |
Definition at line 37 of file RiscVEncoding.h.
#define IRQ_S_GEXT 12 |
Definition at line 40 of file RiscVEncoding.h.
#define IRQ_S_SOFT 1 |
Definition at line 31 of file RiscVEncoding.h.
#define IRQ_S_TIMER 5 |
Definition at line 34 of file RiscVEncoding.h.
#define IRQ_VS_EXT 10 |
Definition at line 38 of file RiscVEncoding.h.
#define IRQ_VS_SOFT 2 |
Definition at line 32 of file RiscVEncoding.h.
#define IRQ_VS_TIMER 6 |
Definition at line 35 of file RiscVEncoding.h.
#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) |
Definition at line 53 of file RiscVEncoding.h.
#define MIP_MEIP (1UL << IRQ_M_EXT) |
Definition at line 51 of file RiscVEncoding.h.
#define MIP_MSIP (1UL << IRQ_M_SOFT) |
Definition at line 45 of file RiscVEncoding.h.
#define MIP_MTIP (1UL << IRQ_M_TIMER) |
Definition at line 48 of file RiscVEncoding.h.
#define MIP_SEIP (1UL << IRQ_S_EXT) |
Definition at line 49 of file RiscVEncoding.h.
#define MIP_SGEIP (1UL << IRQ_S_GEXT) |
Definition at line 52 of file RiscVEncoding.h.
#define MIP_SSIP (1UL << IRQ_S_SOFT) |
Definition at line 43 of file RiscVEncoding.h.
#define MIP_STIP (1UL << IRQ_S_TIMER) |
Definition at line 46 of file RiscVEncoding.h.
#define MIP_VSEIP (1UL << IRQ_VS_EXT) |
Definition at line 50 of file RiscVEncoding.h.
#define MIP_VSSIP (1UL << IRQ_VS_SOFT) |
Definition at line 44 of file RiscVEncoding.h.
#define MIP_VSTIP (1UL << IRQ_VS_TIMER) |
Definition at line 47 of file RiscVEncoding.h.
#define MSTATUS_FS 0x00006000UL |
Definition at line 23 of file RiscVEncoding.h.
#define MSTATUS_MIE 0x00000008UL |
Definition at line 14 of file RiscVEncoding.h.
#define MSTATUS_MPIE 0x00000080UL |
Definition at line 18 of file RiscVEncoding.h.
#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) |
Definition at line 22 of file RiscVEncoding.h.
#define MSTATUS_MPP_SHIFT 11 |
Definition at line 21 of file RiscVEncoding.h.
#define MSTATUS_SIE 0x00000002UL |
Definition at line 13 of file RiscVEncoding.h.
#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) |
Definition at line 16 of file RiscVEncoding.h.
#define MSTATUS_SPIE_SHIFT 5 |
Definition at line 15 of file RiscVEncoding.h.
#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) |
Definition at line 20 of file RiscVEncoding.h.
#define MSTATUS_SPP_SHIFT 8 |
Definition at line 19 of file RiscVEncoding.h.
#define MSTATUS_UBE 0x00000040UL |
Definition at line 17 of file RiscVEncoding.h.
#define PRV_M 3UL |
Definition at line 60 of file RiscVEncoding.h.
#define PRV_S 1UL |
Definition at line 59 of file RiscVEncoding.h.
#define PRV_U 0UL |
Definition at line 58 of file RiscVEncoding.h.
#define SATP64_ASID 0x0FFFF00000000000ULL |
Definition at line 64 of file RiscVEncoding.h.
#define SATP64_MODE 0xF000000000000000ULL |
Definition at line 62 of file RiscVEncoding.h.
#define SATP64_MODE_SHIFT 60 |
Definition at line 63 of file RiscVEncoding.h.
#define SATP64_PPN 0x00000FFFFFFFFFFFULL |
Definition at line 65 of file RiscVEncoding.h.
#define SATP_MODE SATP64_MODE |
Definition at line 74 of file RiscVEncoding.h.
#define SATP_MODE_OFF 0UL |
Definition at line 67 of file RiscVEncoding.h.
#define SATP_MODE_SV32 1UL |
Definition at line 68 of file RiscVEncoding.h.
#define SATP_MODE_SV39 8UL |
Definition at line 69 of file RiscVEncoding.h.
#define SATP_MODE_SV48 9UL |
Definition at line 70 of file RiscVEncoding.h.
#define SATP_MODE_SV57 10UL |
Definition at line 71 of file RiscVEncoding.h.
#define SATP_MODE_SV64 11UL |
Definition at line 72 of file RiscVEncoding.h.
#define SEED_ENTROPY_MASK 0xffff |
Definition at line 135 of file RiscVEncoding.h.
#define SEED_OPST_BIST 0x00000000 |
Definition at line 131 of file RiscVEncoding.h.
#define SEED_OPST_DEAD 0xc0000000 |
Definition at line 134 of file RiscVEncoding.h.
#define SEED_OPST_ES16 0x80000000 |
Definition at line 133 of file RiscVEncoding.h.
#define SEED_OPST_MASK 0xc0000000 |
Definition at line 130 of file RiscVEncoding.h.
#define SEED_OPST_WAIT 0x40000000 |
Definition at line 132 of file RiscVEncoding.h.
#define SIP_SSIP MIP_SSIP |
Definition at line 55 of file RiscVEncoding.h.
#define SIP_STIP MIP_STIP |
Definition at line 56 of file RiscVEncoding.h.
#define SSTATUS_SIE MSTATUS_SIE |
Definition at line 25 of file RiscVEncoding.h.
#define SSTATUS_SPIE MSTATUS_SPIE |
Definition at line 27 of file RiscVEncoding.h.
#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT |
Definition at line 26 of file RiscVEncoding.h.
#define SSTATUS_SPP MSTATUS_SPP |
Definition at line 29 of file RiscVEncoding.h.
#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT |
Definition at line 28 of file RiscVEncoding.h.