Macros
#define	S3_PCI_LIB_ADDRESS(Bus, Device, Function, Register) (((Register) & 0xfff) \| (((Function) & 0x07) << 12) \| (((Device) & 0x1f) << 15) \| (((Bus) & 0xff) << 20))

Functions
UINT8 EFIAPI	S3PciRead8 (IN UINTN Address)

UINT8 EFIAPI	S3PciWrite8 (IN UINTN Address, IN UINT8 Value)

UINT8 EFIAPI	S3PciOr8 (IN UINTN Address, IN UINT8 OrData)

UINT8 EFIAPI	S3PciAnd8 (IN UINTN Address, IN UINT8 AndData)

UINT8 EFIAPI	S3PciAndThenOr8 (IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData)

UINT8 EFIAPI	S3PciBitFieldRead8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)

UINT8 EFIAPI	S3PciBitFieldWrite8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value)

UINT8 EFIAPI	S3PciBitFieldOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData)

UINT8 EFIAPI	S3PciBitFieldAnd8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData)

UINT8 EFIAPI	S3PciBitFieldAndThenOr8 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData)

UINT16 EFIAPI	S3PciRead16 (IN UINTN Address)

UINT16 EFIAPI	S3PciWrite16 (IN UINTN Address, IN UINT16 Value)

UINT16 EFIAPI	S3PciOr16 (IN UINTN Address, IN UINT16 OrData)

UINT16 EFIAPI	S3PciAnd16 (IN UINTN Address, IN UINT16 AndData)

UINT16 EFIAPI	S3PciAndThenOr16 (IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData)

UINT16 EFIAPI	S3PciBitFieldRead16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)

UINT16 EFIAPI	S3PciBitFieldWrite16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value)

UINT16 EFIAPI	S3PciBitFieldOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData)

UINT16 EFIAPI	S3PciBitFieldAnd16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData)

UINT16 EFIAPI	S3PciBitFieldAndThenOr16 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData)

UINT32 EFIAPI	S3PciRead32 (IN UINTN Address)

UINT32 EFIAPI	S3PciWrite32 (IN UINTN Address, IN UINT32 Value)

UINT32 EFIAPI	S3PciOr32 (IN UINTN Address, IN UINT32 OrData)

UINT32 EFIAPI	S3PciAnd32 (IN UINTN Address, IN UINT32 AndData)

UINT32 EFIAPI	S3PciAndThenOr32 (IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData)

UINT32 EFIAPI	S3PciBitFieldRead32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)

UINT32 EFIAPI	S3PciBitFieldWrite32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value)

UINT32 EFIAPI	S3PciBitFieldOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData)

UINT32 EFIAPI	S3PciBitFieldAnd32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData)

UINT32 EFIAPI	S3PciBitFieldAndThenOr32 (IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData)

UINTN EFIAPI	S3PciReadBuffer (IN UINTN StartAddress, IN UINTN Size, OUT VOID *Buffer)

UINTN EFIAPI	S3PciWriteBuffer (IN UINTN StartAddress, IN UINTN Size, IN VOID *Buffer)

Detailed Description

The PCI configuration Library Services that carry out PCI configuration and enable the PCI operations to be replayed during an S3 resume. This library class maps directly on top of the PciLib class.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file S3PciLib.h.

Macro Definition Documentation

◆ S3_PCI_LIB_ADDRESS

#define S3_PCI_LIB_ADDRESS	(	Bus,
		Device,
		Function,
		Register
	)	(((Register) & 0xfff) \| (((Function) & 0x07) << 12) \| (((Device) & 0x1f) << 15) \| (((Bus) & 0xff) << 20))

Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an address that can be passed to the S3 PCI Library functions.

Parameters

Bus	The PCI Bus number. Range 0..255.
Device	The PCI Device number. Range 0..31.
Function	The PCI Function number. Range 0..7.
Register	The PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.

Returns: The encoded PCI address.

Definition at line 28 of file S3PciLib.h.

Function Documentation

◆ S3PciAnd16()

UINT16 EFIAPI S3PciAnd16	(	IN UINTN	Address,
		IN UINT16	AndData
	)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 554 of file S3PciLib.c.

◆ S3PciAnd32()

UINT32 EFIAPI S3PciAnd32	(	IN UINTN	Address,
		IN UINT32	AndData
	)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 930 of file S3PciLib.c.

◆ S3PciAnd8()

UINT8 EFIAPI S3PciAnd8	(	IN UINTN	Address,
		IN UINT8	AndData
	)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 184 of file S3PciLib.c.

◆ S3PciAndThenOr16()

UINT16 EFIAPI S3PciAndThenOr16	(	IN UINTN	Address,
		IN UINT16	AndData,
		IN UINT16	OrData
	)

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	AndData	The value to AND with the PCI configuration register.
[in]	OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, followed a bitwise OR with another 16-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
AndData	The value to AND with the PCI configuration register.
OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Definition at line 588 of file S3PciLib.c.

◆ S3PciAndThenOr32()

UINT32 EFIAPI S3PciAndThenOr32	(	IN UINTN	Address,
		IN UINT32	AndData,
		IN UINT32	OrData
	)

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	AndData	The value to AND with the PCI configuration register.
[in]	OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, followed a bitwise OR with another 32-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
AndData	The value to AND with the PCI configuration register.
OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Definition at line 964 of file S3PciLib.c.

◆ S3PciAndThenOr8()

UINT8 EFIAPI S3PciAndThenOr8	(	IN UINTN	Address,
		IN UINT8	AndData,
		IN UINT8	OrData
	)

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	AndData	The value to AND with the PCI configuration register.
[in]	OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, followed a bitwise OR with another 8-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
AndData	The value to AND with the PCI configuration register.
OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Definition at line 217 of file S3PciLib.c.

◆ S3PciBitFieldAnd16()

UINT16 EFIAPI S3PciBitFieldAnd16	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT16	AndData
	)

Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
[in]	AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 16-bit register and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 741 of file S3PciLib.c.

◆ S3PciBitFieldAnd32()

UINT32 EFIAPI S3PciBitFieldAnd32	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT32	AndData
	)

Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
[in]	AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 1117 of file S3PciLib.c.

◆ S3PciBitFieldAnd8()

UINT8 EFIAPI S3PciBitFieldAnd8	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT8	AndData
	)

Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
[in]	AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 8-bit register and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in AndData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
AndData	The value to AND with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 366 of file S3PciLib.c.

◆ S3PciBitFieldAndThenOr16()

UINT16 EFIAPI S3PciBitFieldAndThenOr16	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT16	AndData,
		IN UINT16	OrData
	)

Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
[in]	AndData	The value to AND with the PCI configuration register.
[in]	OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 16-bit port and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
AndData	The value to AND with the PCI configuration register.
OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Definition at line 785 of file S3PciLib.c.

◆ S3PciBitFieldAndThenOr32()

UINT32 EFIAPI S3PciBitFieldAndThenOr32	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT32	AndData,
		IN UINT32	OrData
	)

Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
[in]	AndData	The value to AND with the PCI configuration register.
[in]	OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 32-bit port and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
AndData	The value to AND with the PCI configuration register.
OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Definition at line 1161 of file S3PciLib.c.

◆ S3PciBitFieldAndThenOr8()

UINT8 EFIAPI S3PciBitFieldAndThenOr8	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT8	AndData,
		IN UINT8	OrData
	)

Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
[in]	AndData	The value to AND with the PCI configuration register.
[in]	OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a bitwise OR, and writes the result back to the bit field in the 8-bit port and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in both AndData and OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
AndData	The value to AND with the PCI configuration register.
OrData	The value to OR with the result of the AND operation.

Returns: The value written back to the PCI configuration register.

Definition at line 409 of file S3PciLib.c.

◆ S3PciBitFieldOr16()

UINT16 EFIAPI S3PciBitFieldOr16	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT16	OrData
	)

Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
[in]	OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 16-bit port and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 700 of file S3PciLib.c.

◆ S3PciBitFieldOr32()

UINT32 EFIAPI S3PciBitFieldOr32	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT32	OrData
	)

Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
[in]	OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 32-bit port and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 1076 of file S3PciLib.c.

◆ S3PciBitFieldOr8()

UINT8 EFIAPI S3PciBitFieldOr8	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT8	OrData
	)

Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
[in]	OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and writes the result back to the bit field in the 8-bit port and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. Extra left bits in OrData are stripped.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 326 of file S3PciLib.c.

◆ S3PciBitFieldRead16()

UINT16 EFIAPI S3PciBitFieldRead16	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit
	)

Reads a bit field of a PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to read.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.

Returns: The value of the bit field read from the PCI configuration register.

Reads a bit field of a PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Reads the bit field in a 16-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters

Address	PCI configuration register to read.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.

Returns: The value of the bit field read from the PCI configuration register.

Definition at line 622 of file S3PciLib.c.

◆ S3PciBitFieldRead32()

UINT32 EFIAPI S3PciBitFieldRead32	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit
	)

Reads a bit field of a PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to read.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.

Returns: The value of the bit field read from the PCI configuration register.

Reads a bit field of a PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Reads the bit field in a 32-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters

Address	PCI configuration register to read.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.

Returns: The value of the bit field read from the PCI configuration register.

Definition at line 998 of file S3PciLib.c.

◆ S3PciBitFieldRead8()

UINT8 EFIAPI S3PciBitFieldRead8	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit
	)

Reads a bit field of a PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to read.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.

Returns: The value of the bit field read from the PCI configuration register.

Reads a bit field of a PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Reads the bit field in an 8-bit PCI configuration register. The bit field is specified by the StartBit and the EndBit. The value of the bit field is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT().

Parameters

Address	PCI configuration register to read.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.

Returns: The value of the bit field read from the PCI configuration register.

Definition at line 250 of file S3PciLib.c.

◆ S3PciBitFieldWrite16()

UINT16 EFIAPI S3PciBitFieldWrite16	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT16	Value
	)

Writes a bit field to a PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
[in]	Value	New value of the bit field.

Returns: The value written back to the PCI configuration register.

Writes a bit field to a PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 16-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..15.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..15.
Value	New value of the bit field.

Returns: The value written back to the PCI configuration register.

Definition at line 659 of file S3PciLib.c.

◆ S3PciBitFieldWrite32()

UINT32 EFIAPI S3PciBitFieldWrite32	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT32	Value
	)

Writes a bit field to a PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
[in]	Value	New value of the bit field.

Returns: The value written back to the PCI configuration register.

Writes a bit field to a PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 32-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..31.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..31.
Value	New value of the bit field.

Returns: The value written back to the PCI configuration register.

Definition at line 1035 of file S3PciLib.c.

◆ S3PciBitFieldWrite8()

UINT8 EFIAPI S3PciBitFieldWrite8	(	IN UINTN	Address,
		IN UINTN	StartBit,
		IN UINTN	EndBit,
		IN UINT8	Value
	)

Writes a bit field to a PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

[in]	Address	The PCI configuration register to write.
[in]	StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
[in]	EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
[in]	Value	New value of the bit field.

Returns: The value written back to the PCI configuration register.

Writes a bit field to a PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Writes Value to the bit field of the PCI configuration register. The bit field is specified by the StartBit and the EndBit. All other bits in the destination PCI configuration register are preserved. The new value of the 8-bit register is returned.

If Address > 0x0FFFFFFF, then ASSERT(). If StartBit is greater than 7, then ASSERT(). If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().

Parameters

Address	PCI configuration register to write.
StartBit	The ordinal of the least significant bit in the bit field. Range 0..7.
EndBit	The ordinal of the most significant bit in the bit field. Range 0..7.
Value	New value of the bit field.

Returns: The value written back to the PCI configuration register.

Definition at line 286 of file S3PciLib.c.

◆ S3PciOr16()

UINT16 EFIAPI S3PciOr16	(	IN UINTN	Address,
		IN UINT16	OrData
	)

Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 16-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 523 of file S3PciLib.c.

◆ S3PciOr32()

UINT32 EFIAPI S3PciOr32	(	IN UINTN	Address,
		IN UINT32	OrData
	)

Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 32-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 899 of file S3PciLib.c.

◆ S3PciOr8()

UINT8 EFIAPI S3PciOr8	(	IN UINTN	Address,
		IN UINT8	OrData
	)

Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value and saves the value in the S3 script to be replayed on S3 resume.

Reads the 8-bit PCI configuration register specified by Address, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
OrData	The value to OR with the PCI configuration register.

Returns: The value written back to the PCI configuration register.

Definition at line 154 of file S3PciLib.c.

◆ S3PciRead16()

UINT16 EFIAPI S3PciRead16 ( IN UINTN Address )

Reads a 16-bit PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

[in] Address The address that encodes the PCI Bus, Device, Function and Register.

Returns: The read value from the PCI configuration register.

Reads a 16-bit PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Reads and returns the 16-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

Address Address that encodes the PCI Bus, Device, Function and Register.

Returns: The read value from the PCI configuration register.

Definition at line 465 of file S3PciLib.c.

◆ S3PciRead32()

UINT32 EFIAPI S3PciRead32 ( IN UINTN Address )

Reads a 32-bit PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

[in] Address The address that encodes the PCI Bus, Device, Function and Register.

Returns: The read value from the PCI configuration register.

Reads a 32-bit PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Reads and returns the 32-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

Address Address that encodes the PCI Bus, Device, Function and Register.

Returns: The read value from the PCI configuration register.

Definition at line 841 of file S3PciLib.c.

◆ S3PciRead8()

UINT8 EFIAPI S3PciRead8 ( IN UINTN Address )

Reads and returns the 8-bit PCI configuration register specified by Address, and saves the value in the S3 script to be replayed on S3 resume. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

[in] Address The address that encodes the PCI Bus, Device, Function and Register.

Returns: The value read from the PCI configuration register.

Reads an 8-bit PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Reads and returns the 8-bit PCI configuration register specified by Address. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

Address Address that encodes the PCI Bus, Device, Function and Register.

Returns: The read value from the PCI configuration register.

Definition at line 98 of file S3PciLib.c.

◆ S3PciReadBuffer()

UINTN EFIAPI S3PciReadBuffer	(	IN UINTN	StartAddress,
		IN UINTN	Size,
		OUT VOID *	Buffer
	)

Reads a range of PCI configuration registers into a caller supplied buffer, and saves the value in the S3 script to be replayed on S3 resume.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters

[in]	StartAddress	Starting address that encodes the PCI Bus, Device, Function and Register.
[in]	Size	Size in bytes of the transfer.
[out]	Buffer	The pointer to a buffer receiving the data read.

Returns: Size.

Reads a range of PCI configuration registers into a caller supplied buffer and saves the value in the S3 script to be replayed on S3 resume.

Reads the range of PCI configuration registers specified by StartAddress and Size into the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be read. Size is returned. When possible 32-bit PCI configuration read cycles are used to read from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters

StartAddress	Starting address that encodes the PCI Bus, Device, Function and Register.
Size	Size in bytes of the transfer.
Buffer	Pointer to a buffer receiving the data read.

Returns: Size

Definition at line 1198 of file S3PciLib.c.

◆ S3PciWrite16()

UINT16 EFIAPI S3PciWrite16	(	IN UINTN	Address,
		IN UINT16	Value
	)

Writes a 16-bit PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	Value	The value to write.

Returns: The value written to the PCI configuration register.

Writes a 16-bit PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
Value	The value to write.

Returns: The value written to the PCI configuration register.

Definition at line 492 of file S3PciLib.c.

◆ S3PciWrite32()

UINT32 EFIAPI S3PciWrite32	(	IN UINTN	Address,
		IN UINT32	Value
	)

Writes a 32-bit PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	Value	The value to write.

Returns: The value written to the PCI configuration register.

Writes a 32-bit PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
Value	The value to write.

Returns: The value written to the PCI configuration register.

Definition at line 868 of file S3PciLib.c.

◆ S3PciWrite8()

UINT8 EFIAPI S3PciWrite8	(	IN UINTN	Address,
		IN UINT8	Value
	)

Writes an 8-bit PCI configuration register, and saves the value in the S3 script to be replayed on S3 resume.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

[in]	Address	The address that encodes the PCI Bus, Device, Function and Register.
[in]	Value	The value to write.

Returns: The value written to the PCI configuration register.

Writes an 8-bit PCI configuration register and saves the value in the S3 script to be replayed on S3 resume.

Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. Value is returned. This function must guarantee that all PCI read and write operations are serialized.

If Address > 0x0FFFFFFF, then ASSERT().

Parameters

Address	Address that encodes the PCI Bus, Device, Function and Register.
Value	The value to write.

Returns: The value written to the PCI configuration register.

Definition at line 124 of file S3PciLib.c.

◆ S3PciWriteBuffer()

UINTN EFIAPI S3PciWriteBuffer	(	IN UINTN	StartAddress,
		IN UINTN	Size,
		IN VOID *	Buffer
	)

Copies the data in a caller supplied buffer to a specified range of PCI configuration space, and saves the value in the S3 script to be replayed on S3 resume.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters

[in]	StartAddress	Starting address that encodes the PCI Bus, Device, Function and Register.
[in]	Size	Size in bytes of the transfer.
[in]	Buffer	The pointer to a buffer containing the data to write.

Returns: Size.

Copies the data in a caller supplied buffer to a specified range of PCI configuration space and saves the value in the S3 script to be replayed on S3 resume.

Writes the range of PCI configuration registers specified by StartAddress and Size from the buffer specified by Buffer. This function only allows the PCI configuration registers from a single PCI function to be written. Size is returned. When possible 32-bit PCI configuration write cycles are used to write from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range.

If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT().

Parameters

StartAddress	Starting address that encodes the PCI Bus, Device, Function and Register.
Size	Size in bytes of the transfer.
Buffer	Pointer to a buffer containing the data to write.

Returns: Size

Definition at line 1244 of file S3PciLib.c.

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ S3_PCI_LIB_ADDRESS

Function Documentation

◆ S3PciAnd16()

◆ S3PciAnd32()

◆ S3PciAnd8()

◆ S3PciAndThenOr16()

◆ S3PciAndThenOr32()

◆ S3PciAndThenOr8()

◆ S3PciBitFieldAnd16()

◆ S3PciBitFieldAnd32()

◆ S3PciBitFieldAnd8()

◆ S3PciBitFieldAndThenOr16()

◆ S3PciBitFieldAndThenOr32()

◆ S3PciBitFieldAndThenOr8()

◆ S3PciBitFieldOr16()

◆ S3PciBitFieldOr32()

◆ S3PciBitFieldOr8()

◆ S3PciBitFieldRead16()

◆ S3PciBitFieldRead32()

◆ S3PciBitFieldRead8()

◆ S3PciBitFieldWrite16()

◆ S3PciBitFieldWrite32()

◆ S3PciBitFieldWrite8()

◆ S3PciOr16()

◆ S3PciOr32()

◆ S3PciOr8()

◆ S3PciRead16()

◆ S3PciRead32()

◆ S3PciRead8()

◆ S3PciReadBuffer()

◆ S3PciWrite16()

◆ S3PciWrite32()

◆ S3PciWrite8()

◆ S3PciWriteBuffer()