TianoCore EDK2 master
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SdMmcOverride.h
Go to the documentation of this file.
1
11#ifndef __SD_MMC_OVERRIDE_H__
12#define __SD_MMC_OVERRIDE_H__
13
15
16#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
17 { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } }
18
19#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x3
20
22
23#define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8
24#define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32
25#define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE MAX_UINT8
26
27typedef enum {
28 SdDriverStrengthTypeB = 0,
29 SdDriverStrengthTypeA,
30 SdDriverStrengthTypeC,
31 SdDriverStrengthTypeD,
32 SdDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE
33} SD_DRIVER_STRENGTH_TYPE;
34
35typedef enum {
36 EmmcDriverStrengthType0 = 0,
37 EmmcDriverStrengthType1,
38 EmmcDriverStrengthType2,
39 EmmcDriverStrengthType3,
40 EmmcDriverStrengthType4,
41 EmmcDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE
42} EMMC_DRIVER_STRENGTH_TYPE;
43
44typedef union {
45 SD_DRIVER_STRENGTH_TYPE Sd;
46 EMMC_DRIVER_STRENGTH_TYPE Emmc;
48
49typedef struct {
50 //
51 // The target width of the bus. If user tells driver to ignore it
52 // or specifies unsupported width driver will choose highest supported
53 // bus width for a given mode.
54 //
55 UINT8 BusWidth;
56 //
57 // The target clock frequency of the bus in MHz. If user tells driver to ignore
58 // it or specifies unsupported frequency driver will choose highest supported
59 // clock frequency for a given mode.
60 //
61 UINT32 ClockFreq;
62 //
63 // The target driver strength of the bus. If user tells driver to
64 // ignore it or specifies unsupported driver strength, driver will
65 // default to Type0 for eMMC cards and TypeB for SD cards. Driver strength
66 // setting is only considered if chosen bus timing supports them.
67 //
68 EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
70
71typedef enum {
72 SdMmcSdDs,
73 SdMmcSdHs,
74 SdMmcUhsSdr12,
75 SdMmcUhsSdr25,
76 SdMmcUhsSdr50,
77 SdMmcUhsDdr50,
78 SdMmcUhsSdr104,
79 SdMmcMmcLegacy,
80 SdMmcMmcHsSdr,
81 SdMmcMmcHsDdr,
82 SdMmcMmcHs200,
83 SdMmcMmcHs400,
84} SD_MMC_BUS_MODE;
85
86typedef enum {
87 EdkiiSdMmcResetPre,
88 EdkiiSdMmcResetPost,
89 EdkiiSdMmcInitHostPre,
90 EdkiiSdMmcInitHostPost,
91 EdkiiSdMmcUhsSignaling,
92 EdkiiSdMmcSwitchClockFreqPost,
93 EdkiiSdMmcGetOperatingParam
94} EDKII_SD_MMC_PHASE_TYPE;
95
110typedef
113 IN EFI_HANDLE ControllerHandle,
114 IN UINT8 Slot,
115 IN OUT VOID *SdMmcHcSlotCapability,
116 IN OUT UINT32 *BaseClkFreq
117 );
118
134typedef
137 IN EFI_HANDLE ControllerHandle,
138 IN UINT8 Slot,
139 IN EDKII_SD_MMC_PHASE_TYPE PhaseType,
140 IN OUT VOID *PhaseData
141 );
142
144 //
145 // Protocol version of this implementation
146 //
147 UINTN Version;
148 //
149 // Callback to override SD/MMC host controller capability bits
150 //
151 EDKII_SD_MMC_CAPABILITY Capability;
152 //
153 // Callback to invoke SD/MMC override hooks
154 //
155 EDKII_SD_MMC_NOTIFY_PHASE NotifyPhase;
156};
157
158extern EFI_GUID gEdkiiSdMmcOverrideProtocolGuid;
159
160#endif
UINT64 UINTN
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
EFI_STATUS(EFIAPI * EDKII_SD_MMC_NOTIFY_PHASE)(IN EFI_HANDLE ControllerHandle, IN UINT8 Slot, IN EDKII_SD_MMC_PHASE_TYPE PhaseType, IN OUT VOID *PhaseData)
EFI_STATUS(EFIAPI * EDKII_SD_MMC_CAPABILITY)(IN EFI_HANDLE ControllerHandle, IN UINT8 Slot, IN OUT VOID *SdMmcHcSlotCapability, IN OUT UINT32 *BaseClkFreq)
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
VOID * EFI_HANDLE
Definition: UefiBaseType.h:33
Definition: Base.h:213