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SdMmcPciHcPei.c
Go to the documentation of this file.
1
10#include "SdMmcPciHcPei.h"
11
12EDKII_SD_MMC_HOST_CONTROLLER_PPI mSdMmcHostControllerPpi = { GetSdMmcHcMmioBar };
13
14EFI_PEI_PPI_DESCRIPTOR mPpiList = {
15 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
16 &gEdkiiPeiSdMmcHostControllerPpiGuid,
17 &mSdMmcHostControllerPpi
18};
19
35EFIAPI
38 IN UINT8 ControllerId,
39 IN OUT UINTN **MmioBar,
40 OUT UINT8 *BarNum
41 )
42{
44
45 if ((This == NULL) || (MmioBar == NULL) || (BarNum == NULL)) {
46 return EFI_INVALID_PARAMETER;
47 }
48
49 Private = SD_MMC_HC_PEI_PRIVATE_DATA_FROM_THIS (This);
50
51 if (ControllerId >= Private->TotalSdMmcHcs) {
52 return EFI_INVALID_PARAMETER;
53 }
54
55 *MmioBar = &Private->MmioBar[ControllerId].MmioBarAddr[0];
56 *BarNum = (UINT8)Private->MmioBar[ControllerId].SlotNum;
57 return EFI_SUCCESS;
58}
59
71EFIAPI
73 IN EFI_PEI_FILE_HANDLE FileHandle,
74 IN CONST EFI_PEI_SERVICES **PeiServices
75 )
76{
77 EFI_BOOT_MODE BootMode;
78 EFI_STATUS Status;
79 UINT16 Bus;
80 UINT16 Device;
81 UINT16 Function;
82 UINT32 Size;
83 UINT64 MmioSize;
84 UINT8 SubClass;
85 UINT8 BaseClass;
86 UINT8 SlotInfo;
87 UINT8 SlotNum;
88 UINT8 FirstBar;
89 UINT8 Index;
90 UINT8 Slot;
91 UINT32 BarAddr;
93
94 //
95 // Shadow this PEIM to run from memory
96 //
97 if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {
98 return EFI_SUCCESS;
99 }
100
101 Status = PeiServicesGetBootMode (&BootMode);
105 if (BootMode == BOOT_ON_S3_RESUME) {
106 return EFI_SUCCESS;
107 }
108
110 if (Private == NULL) {
111 DEBUG ((DEBUG_ERROR, "Failed to allocate memory for SD_MMC_HC_PEI_PRIVATE_DATA! \n"));
112 return EFI_OUT_OF_RESOURCES;
113 }
114
115 Private->Signature = SD_MMC_HC_PEI_SIGNATURE;
116 Private->SdMmcHostControllerPpi = mSdMmcHostControllerPpi;
117 Private->PpiList = mPpiList;
118 Private->PpiList.Ppi = &Private->SdMmcHostControllerPpi;
119
120 BarAddr = PcdGet32 (PcdSdMmcPciHostControllerMmioBase);
121 for (Bus = 0; Bus < 256; Bus++) {
122 for (Device = 0; Device < 32; Device++) {
123 for (Function = 0; Function < 8; Function++) {
124 SubClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0A));
125 BaseClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0B));
126
127 if ((SubClass == PCI_SUBCLASS_SD_HOST_CONTROLLER) && (BaseClass == PCI_CLASS_SYSTEM_PERIPHERAL)) {
128 //
129 // Get the SD/MMC Pci host controller's Slot Info.
130 //
131 SlotInfo = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, SD_MMC_HC_PEI_SLOT_OFFSET));
132 FirstBar = (*(SD_MMC_HC_PEI_SLOT_INFO *)&SlotInfo).FirstBar;
133 SlotNum = (*(SD_MMC_HC_PEI_SLOT_INFO *)&SlotInfo).SlotNum + 1;
134 ASSERT ((FirstBar + SlotNum) < MAX_SD_MMC_SLOTS);
135
136 for (Index = 0, Slot = FirstBar; Slot < (FirstBar + SlotNum); Index++, Slot++) {
137 //
138 // Get the SD/MMC Pci host controller's MMIO region size.
139 //
140 PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16) ~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
141 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), 0xFFFFFFFF);
142 Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot));
143
144 switch (Size & 0x07) {
145 case 0x0:
146 //
147 // Memory space: anywhere in 32 bit address space
148 //
149 MmioSize = (~(Size & 0xFFFFFFF0)) + 1;
150 break;
151 case 0x4:
152 //
153 // Memory space: anywhere in 64 bit address space
154 //
155 MmioSize = Size & 0xFFFFFFF0;
156 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);
157 Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4));
158 //
159 // Fix the length to support some spefic 64 bit BAR
160 //
161 Size |= ((UINT32)(-1) << HighBitSet32 (Size));
162 //
163 // Calculate the size of 64bit bar
164 //
165 MmioSize |= LShiftU64 ((UINT64)Size, 32);
166 MmioSize = (~(MmioSize)) + 1;
167 //
168 // Clean the high 32bits of this 64bit BAR to 0 as we only allow a 32bit BAR.
169 //
170 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot + 4), 0);
171 break;
172 default:
173 //
174 // Unknown BAR type
175 //
176 ASSERT (FALSE);
177 continue;
178 }
179
180 //
181 // Assign resource to the SdMmc Pci host controller's MMIO BAR.
182 // Enable the SdMmc Pci host controller by setting BME and MSE bits of PCI_CMD register.
183 //
184 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET + 4 * Slot), BarAddr);
185 PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
186 //
187 // Record the allocated Mmio base address.
188 //
189 Private->MmioBar[Private->TotalSdMmcHcs].SlotNum++;
190 Private->MmioBar[Private->TotalSdMmcHcs].MmioBarAddr[Index] = BarAddr;
191 BarAddr += (UINT32)MmioSize;
192 }
193
194 Private->TotalSdMmcHcs++;
195 ASSERT (Private->TotalSdMmcHcs < MAX_SD_MMC_HCS);
196 }
197 }
198 }
199 }
200
204 Status = PeiServicesInstallPpi (&Private->PpiList);
205
206 ASSERT_EFI_ERROR (Status);
207 return Status;
208}
UINT64 UINTN
UINT64 EFIAPI LShiftU64(IN UINT64 Operand, IN UINTN Count)
Definition: LShiftU64.c:28
INTN EFIAPI HighBitSet32(IN UINT32 Operand)
Definition: HighBitSet32.c:27
VOID *EFIAPI AllocateZeroPool(IN UINTN AllocationSize)
EFI_STATUS EFIAPI PeiServicesGetBootMode(OUT EFI_BOOT_MODE *BootMode)
EFI_STATUS EFIAPI PeiServicesInstallPpi(IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList)
EFI_STATUS EFIAPI PeiServicesRegisterForShadow(IN EFI_PEI_FILE_HANDLE FileHandle)
#define NULL
Definition: Base.h:319
#define CONST
Definition: Base.h:259
#define FALSE
Definition: Base.h:307
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
#define ASSERT_EFI_ERROR(StatusParameter)
Definition: DebugLib.h:462
#define DEBUG(Expression)
Definition: DebugLib.h:434
UINT32 EFIAPI PciRead32(IN UINTN Address)
Definition: PciLib.c:739
UINT8 EFIAPI PciRead8(IN UINTN Address)
Definition: PciLib.c:62
#define PCI_LIB_ADDRESS(Bus, Device, Function, Register)
Definition: PciLib.h:34
UINT16 EFIAPI PciAnd16(IN UINTN Address, IN UINT16 AndData)
Definition: PciLib.c:484
UINT32 EFIAPI PciWrite32(IN UINTN Address, IN UINT32 Value)
Definition: PciLib.c:765
UINT16 EFIAPI PciOr16(IN UINTN Address, IN UINT16 OrData)
Definition: PciLib.c:453
#define PcdGet32(TokenName)
Definition: PcdLib.h:362
#define EFI_PCI_COMMAND_MEMORY_SPACE
0x0002
Definition: Pci22.h:592
#define EFI_PCI_COMMAND_BUS_MASTER
0x0004
Definition: Pci22.h:593
UINT32 EFI_BOOT_MODE
Definition: PiBootMode.h:18
VOID * EFI_PEI_FILE_HANDLE
Definition: PiPeiCis.h:26
EFI_STATUS EFIAPI GetSdMmcHcMmioBar(IN EDKII_SD_MMC_HOST_CONTROLLER_PPI *This, IN UINT8 ControllerId, IN OUT UINTN **MmioBar, OUT UINT8 *BarNum)
Definition: SdMmcPciHcPei.c:36
EFI_STATUS EFIAPI InitializeSdMmcHcPeim(IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Definition: SdMmcPciHcPei.c:72
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
#define EFI_SUCCESS
Definition: UefiBaseType.h:112