SdramSpdDdr3.h

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#ifndef _SDRAM_SPD_DDR3_H_
#define _SDRAM_SPD_DDR3_H_
 
#pragma pack (push, 1)
 
typedef union {
  struct {
    UINT8    BytesUsed   :  4;                       
    UINT8    BytesTotal  :  3;                       
    UINT8    CrcCoverage :  1;                       
  } Bits;
  UINT8    Data;
} SPD3_DEVICE_DESCRIPTION_STRUCT;
 
typedef union {
  struct {
    UINT8    Minor :  4;                             
    UINT8    Major :  4;                             
  } Bits;
  UINT8    Data;
} SPD3_REVISION_STRUCT;
 
typedef union {
  struct {
    UINT8    Type :  8;                              
  } Bits;
  UINT8    Data;
} SPD3_DRAM_DEVICE_TYPE_STRUCT;
 
typedef union {
  struct {
    UINT8    ModuleType :  4;                        
    UINT8    Reserved   :  4;                        
  } Bits;
  UINT8    Data;
} SPD3_MODULE_TYPE_STRUCT;
 
typedef union {
  struct {
    UINT8    Density     :  4;                       
    UINT8    BankAddress :  3;                       
    UINT8    Reserved    :  1;                       
  } Bits;
  UINT8    Data;
} SPD3_SDRAM_DENSITY_BANKS_STRUCT;
 
typedef union {
  struct {
    UINT8    ColumnAddress :  3;                     
    UINT8    RowAddress    :  3;                     
    UINT8    Reserved      :  2;                     
  } Bits;
  UINT8    Data;
} SPD3_SDRAM_ADDRESSING_STRUCT;
 
typedef union {
  struct {
    UINT8    OperationAt1_50 :  1;                   
    UINT8    OperationAt1_35 :  1;                   
    UINT8    OperationAt1_25 :  1;                   
    UINT8    Reserved        :  5;                   
  } Bits;
  UINT8    Data;
} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;
 
typedef union {
  struct {
    UINT8    SdramDeviceWidth :  3;                  
    UINT8    RankCount        :  3;                  
    UINT8    Reserved         :  2;                  
  } Bits;
  UINT8    Data;
} SPD3_MODULE_ORGANIZATION_STRUCT;
 
typedef union {
  struct {
    UINT8    PrimaryBusWidth   :  3;                 
    UINT8    BusWidthExtension :  2;                 
    UINT8    Reserved          :  3;                 
  } Bits;
  UINT8    Data;
} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;
 
typedef union {
  struct {
    UINT8    Divisor  :  4;                          
    UINT8    Dividend :  4;                          
  } Bits;
  UINT8    Data;
} SPD3_FINE_TIMEBASE_STRUCT;
 
typedef union {
  struct {
    UINT8    Dividend :  8;                          
  } Bits;
  UINT8    Data;
} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
 
typedef union {
  struct {
    UINT8    Divisor :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
 
typedef struct {
  SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT    Dividend; 
  SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT     Divisor;  
} SPD3_MEDIUM_TIMEBASE;
 
typedef union {
  struct {
    UINT8    tCKmin :  8;                            
  } Bits;
  UINT8    Data;
} SPD3_TCK_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT16    Cl4      :  1;                         
    UINT16    Cl5      :  1;                         
    UINT16    Cl6      :  1;                         
    UINT16    Cl7      :  1;                         
    UINT16    Cl8      :  1;                         
    UINT16    Cl9      :  1;                         
    UINT16    Cl10     :  1;                         
    UINT16    Cl11     :  1;                         
    UINT16    Cl12     :  1;                         
    UINT16    Cl13     :  1;                         
    UINT16    Cl14     :  1;                         
    UINT16    Cl15     :  1;                         
    UINT16    Cl16     :  1;                         
    UINT16    Cl17     :  1;                         
    UINT16    Cl18     :  1;                         
    UINT16    Reserved :  1;                         
  } Bits;
  UINT16    Data;
  UINT8     Data8[2];
} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;
 
typedef union {
  struct {
    UINT8    tAAmin :  8;                            
  } Bits;
  UINT8    Data;
} SPD3_TAA_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tWRmin :  8;                            
  } Bits;
  UINT8    Data;
} SPD3_TWR_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRCDmin :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_TRCD_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRRDmin :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_TRRD_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRPmin :  8;                            
  } Bits;
  UINT8    Data;
} SPD3_TRP_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRASminUpper :  4;                      
    UINT8    tRCminUpper  :  4;                      
  } Bits;
  UINT8    Data;
} SPD3_TRAS_TRC_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRASmin :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_TRAS_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRCmin :  8;                            
  } Bits;
  UINT8    Data;
} SPD3_TRC_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT16    tRFCmin :  16;                          
  } Bits;
  UINT16    Data;
  UINT8     Data8[2];
} SPD3_TRFC_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tWTRmin :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_TWTR_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tRTPmin :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_TRTP_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    tFAWminUpper :  4;                      
    UINT8    Reserved     :  4;                      
  } Bits;
  UINT8    Data;
} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;
 
typedef union {
  struct {
    UINT8    tFAWmin :  8;                           
  } Bits;
  UINT8    Data;
} SPD3_TFAW_MIN_MTB_STRUCT;
 
typedef union {
  struct {
    UINT8    Rzq6     :  1;                          
    UINT8    Rzq7     :  1;                          
    UINT8    Reserved :  5;                          
    UINT8    DllOff   :  1;                          
  } Bits;
  UINT8    Data;
} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;
 
typedef union {
  struct {
    UINT8    ExtendedTemperatureRange       :  1;    
    UINT8    ExtendedTemperatureRefreshRate :  1;    
    UINT8    AutoSelfRefresh                :  1;    
    UINT8    OnDieThermalSensor             :  1;    
    UINT8    Reserved                       :  3;    
    UINT8    PartialArraySelfRefresh        :  1;    
  } Bits;
  UINT8    Data;
} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;
 
typedef union {
  struct {
    UINT8    ThermalSensorAccuracy :  7;             
    UINT8    ThermalSensorPresence :  1;             
  } Bits;
  UINT8    Data;
} SPD3_MODULE_THERMAL_SENSOR_STRUCT;
 
typedef union {
  struct {
    UINT8    SignalLoading   :  2;                   
    UINT8    Reserved        :  2;                   
    UINT8    DieCount        :  3;                   
    UINT8    SdramDeviceType :  1;                   
  } Bits;
  UINT8    Data;
} SPD3_SDRAM_DEVICE_TYPE_STRUCT;
 
typedef union {
  struct {
    INT8    tCKminFine :  8;                         
  } Bits;
  INT8    Data;
} SPD3_TCK_MIN_FTB_STRUCT;
 
typedef union {
  struct {
    INT8    tAAminFine :  8;                         
  } Bits;
  INT8    Data;
} SPD3_TAA_MIN_FTB_STRUCT;
 
typedef union {
  struct {
    INT8    tRCDminFine :  8;                        
  } Bits;
  INT8    Data;
} SPD3_TRCD_MIN_FTB_STRUCT;
 
typedef union {
  struct {
    INT8    tRPminFine :  8;                         
  } Bits;
  INT8    Data;
} SPD3_TRP_MIN_FTB_STRUCT;
 
typedef union {
  struct {
    INT8    tRCminFine :  8;                         
  } Bits;
  INT8    Data;
} SPD3_TRC_MIN_FTB_STRUCT;
 
typedef union {
  struct {
    UINT8    MaximumActivateCount  :  4;             
    UINT8    MaximumActivateWindow :  2;             
    UINT8    VendorSpecific        :  2;             
  } Bits;
  UINT8    Data;
} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;
 
typedef union {
  struct {
    UINT8    Height           :  5;                  
    UINT8    RawCardExtension :  3;                  
  } Bits;
  UINT8    Data;
} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;
 
typedef union {
  struct {
    UINT8    FrontThickness :  4;                    
    UINT8    BackThickness  :  4;                    
  } Bits;
  UINT8    Data;
} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;
 
typedef union {
  struct {
    UINT8    Card      :  5;                         
    UINT8    Revision  :  2;                         
    UINT8    Extension :  1;                         
  } Bits;
  UINT8    Data;
} SPD3_UNBUF_REFERENCE_RAW_CARD;
 
typedef union {
  struct {
    UINT8    MappingRank1 :  1;                      
    UINT8    Reserved     :  7;                      
  } Bits;
  UINT8    Data;
} SPD3_UNBUF_ADDRESS_MAPPING;
 
typedef union {
  struct {
    UINT8    Height   :  5;                          
    UINT8    Reserved :  3;                          
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;
 
typedef union {
  struct {
    UINT8    FrontThickness :  4;                    
    UINT8    BackThickness  :  4;                    
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;
 
typedef union {
  struct {
    UINT8    Card      :  5;                         
    UINT8    Revision  :  2;                         
    UINT8    Extension :  1;                         
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_REFERENCE_RAW_CARD;
 
typedef union {
  struct {
    UINT8    RegisterCount :  2;                     
    UINT8    DramRowCount  :  2;                     
    UINT8    RegisterType  :  4;                     
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_MODULE_ATTRIBUTES;
 
typedef union {
  struct {
    UINT8    HeatSpreaderThermalCharacteristics :  7; 
    UINT8    HeatSpreaderSolution               :  1; 
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;
 
typedef union {
  struct {
    UINT16    ContinuationCount  :  7;               
    UINT16    ContinuationParity :  1;               
    UINT16    LastNonZeroByte    :  8;               
  } Bits;
  UINT16    Data;
  UINT8     Data8[2];
} SPD3_MANUFACTURER_ID_CODE;
 
typedef union {
  struct {
    UINT8    RegisterRevisionNumber;           
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_REGISTER_REVISION_NUMBER;
 
typedef union {
  struct {
    UINT8    Bit0     :  1;                         
    UINT8    Bit1     :  1;                         
    UINT8    Bit2     :  1;                         
    UINT8    Reserved :  5;                         
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_REGISTER_TYPE;
 
typedef union {
  struct {
    UINT8    Reserved               :  4;           
    UINT8    CommandAddressAOutputs :  2;           
    UINT8    CommandAddressBOutputs :  2;           
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;
 
typedef union {
  struct {
    UINT8    ControlSignalsAOutputs :  2;           
    UINT8    ControlSignalsBOutputs :  2;           
    UINT8    Y1Y3ClockOutputs       :  2;           
    UINT8    Y0Y2ClockOutputs       :  2;           
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;
 
typedef union {
  struct {
    UINT8    Reserved0 :  4;                        
    UINT8    Reserved1 :  4;                        
  } Bits;
  UINT8    Data;
} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;
 
typedef union {
  struct {
    UINT8    Height   :  5;                         
    UINT8    Reserved :  3;                         
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;
 
typedef union {
  struct {
    UINT8    FrontThickness :  4;                   
    UINT8    BackThickness  :  4;                   
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;
 
typedef union {
  struct {
    UINT8    Card      :  5;                        
    UINT8    Revision  :  2;                        
    UINT8    Extension :  1;                        
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_REFERENCE_RAW_CARD;
 
typedef union {
  struct {
    UINT8    RegisterCount :  2;                    
    UINT8    DramRowCount  :  2;                    
    UINT8    RegisterType  :  4;                    
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_MODULE_ATTRIBUTES;
 
typedef union {
  struct {
    UINT8    AddressCommandPrelaunch :  1;          
    UINT8    Rank1Rank5Swap          :  1;          
    UINT8    Reserved0               :  1;          
    UINT8    Reserved1               :  1;          
    UINT8    AddressCommandOutputs   :  2;          
    UINT8    QxCS_nOutputs           :  2;          
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;
 
typedef union {
  struct {
    UINT8    QxOdtOutputs     :  2;                 
    UINT8    QxCkeOutputs     :  2;                 
    UINT8    Y1Y3ClockOutputs :  2;                 
    UINT8    Y0Y2ClockOutputs :  2;                 
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;
 
typedef union {
  struct {
    UINT8    YExtendedDelay :  2;                   
    UINT8    QxCS_n         :  2;                   
    UINT8    QxOdt          :  2;                   
    UINT8    QxCke          :  2;                   
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_EXTENDED_DELAY;
 
typedef union {
  struct {
    UINT8    DelayY   :  3;                         
    UINT8    Reserved :  1;                         
    UINT8    QxCS_n   :  4;                         
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;
 
typedef union {
  struct {
    UINT8    QxCS_n :  4;                           
    UINT8    QxOdt  :  4;                           
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;
 
typedef union {
  struct {
    UINT8    RC8MdqOdtStrength :  3;                
    UINT8    RC8Reserved       :  1;                
    UINT8    RC9MdqOdtStrength :  3;                
    UINT8    RC9Reserved       :  1;                
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;
 
typedef union {
  struct {
    UINT8    RC10DA3ValueR0 :  1;                   
    UINT8    RC10DA4ValueR0 :  1;                   
    UINT8    RC10DA3ValueR1 :  1;                   
    UINT8    RC10DA4ValueR1 :  1;                   
    UINT8    RC11DA3ValueR0 :  1;                   
    UINT8    RC11DA4ValueR0 :  1;                   
    UINT8    RC11DA3ValueR1 :  1;                   
    UINT8    RC11DA4ValueR1 :  1;                   
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;
 
typedef union {
  struct {
    UINT8    Driver_Impedance :  2;                 
    UINT8    Rtt_Nom          :  3;                 
    UINT8    Reserved         :  1;                 
    UINT8    Rtt_WR           :  2;                 
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_MR_1_2;
 
typedef union {
  struct {
    UINT8    MinimumDelayTime :  7;                 
    UINT8    Reserved         :  1;                 
  } Bits;
  UINT8    Data;
} SPD3_LRDIMM_MODULE_DELAY_TIME;
 
typedef struct {
  UINT8    Year;                               
  UINT8    Week;                               
} SPD3_MANUFACTURING_DATE;
 
typedef union {
  UINT32    Data;
  UINT16    SerialNumber16[2];
  UINT8     SerialNumber8[4];
} SPD3_MANUFACTURER_SERIAL_NUMBER;
 
typedef struct {
  UINT8    Location;                           
} SPD3_MANUFACTURING_LOCATION;
 
typedef struct {
  SPD3_MANUFACTURER_ID_CODE          IdCode;                     
  SPD3_MANUFACTURING_LOCATION        Location;                   
  SPD3_MANUFACTURING_DATE            Date;                       
  SPD3_MANUFACTURER_SERIAL_NUMBER    SerialNumber;               
} SPD3_UNIQUE_MODULE_ID;
 
typedef union {
  UINT16    Crc[1];
  UINT8     Data8[2];
} SPD3_CYCLIC_REDUNDANCY_CODE;
 
typedef struct {
  SPD3_DEVICE_DESCRIPTION_STRUCT         Description;              
  SPD3_REVISION_STRUCT                   Revision;                 
  SPD3_DRAM_DEVICE_TYPE_STRUCT           DramDeviceType;           
  SPD3_MODULE_TYPE_STRUCT                ModuleType;               
  SPD3_SDRAM_DENSITY_BANKS_STRUCT        SdramDensityAndBanks;     
  SPD3_SDRAM_ADDRESSING_STRUCT           SdramAddressing;          
  SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT     ModuleNominalVoltage;     
  SPD3_MODULE_ORGANIZATION_STRUCT        ModuleOrganization;       
  SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT    ModuleMemoryBusWidth;     
  SPD3_FINE_TIMEBASE_STRUCT              FineTimebase;             
  SPD3_MEDIUM_TIMEBASE                   MediumTimebase;           
  SPD3_TCK_MIN_MTB_STRUCT                tCKmin;                   
  UINT8                                  Reserved0;                
  SPD3_CAS_LATENCIES_SUPPORTED_STRUCT    CasLatencies;             
  SPD3_TAA_MIN_MTB_STRUCT                tAAmin;                   
  SPD3_TWR_MIN_MTB_STRUCT                tWRmin;                   
  SPD3_TRCD_MIN_MTB_STRUCT               tRCDmin;                  
  SPD3_TRRD_MIN_MTB_STRUCT               tRRDmin;                  
  SPD3_TRP_MIN_MTB_STRUCT                tRPmin;                   
  SPD3_TRAS_TRC_MIN_MTB_STRUCT           tRASMintRCMinUpper;       
  SPD3_TRAS_MIN_MTB_STRUCT               tRASmin;                  
  SPD3_TRC_MIN_MTB_STRUCT                tRCmin;                   
  SPD3_TRFC_MIN_MTB_STRUCT               tRFCmin;                  
  SPD3_TWTR_MIN_MTB_STRUCT               tWTRmin;                  
  SPD3_TRTP_MIN_MTB_STRUCT               tRTPmin;                  
  SPD3_TFAW_MIN_MTB_UPPER_STRUCT         tFAWMinUpper;             
  SPD3_TFAW_MIN_MTB_STRUCT               tFAWmin;                  
  SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT    SdramOptionalFeatures;    
  SPD3_SDRAM_THERMAL_REFRESH_STRUCT      ThermalAndRefreshOptions; 
  SPD3_MODULE_THERMAL_SENSOR_STRUCT      ModuleThermalSensor;      
  SPD3_SDRAM_DEVICE_TYPE_STRUCT          SdramDeviceType;          
  SPD3_TCK_MIN_FTB_STRUCT                tCKminFine;               
  SPD3_TAA_MIN_FTB_STRUCT                tAAminFine;               
  SPD3_TRCD_MIN_FTB_STRUCT               tRCDminFine;              
  SPD3_TRP_MIN_FTB_STRUCT                tRPminFine;               
  SPD3_TRC_MIN_FTB_STRUCT                tRCminFine;               
  UINT8                                  Reserved1[40 - 39 + 1];   
  SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT       MacValue;                 
  UINT8                                  Reserved2[59 - 42 + 1];   
} SPD3_BASE_SECTION;
 
typedef struct {
  SPD3_UNBUF_MODULE_NOMINAL_HEIGHT       ModuleNominalHeight;    
  SPD3_UNBUF_MODULE_NOMINAL_THICKNESS    ModuleMaximumThickness; 
  SPD3_UNBUF_REFERENCE_RAW_CARD          ReferenceRawCardUsed;   
  SPD3_UNBUF_ADDRESS_MAPPING             AddressMappingEdgeConn; 
  UINT8                                  Reserved[116 - 64 + 1]; 
} SPD3_MODULE_UNBUFFERED;
 
typedef struct {
  SPD3_RDIMM_MODULE_NOMINAL_HEIGHT               ModuleNominalHeight;         
  SPD3_RDIMM_MODULE_NOMINAL_THICKNESS            ModuleMaximumThickness;      
  SPD3_RDIMM_REFERENCE_RAW_CARD                  ReferenceRawCardUsed;        
  SPD3_RDIMM_MODULE_ATTRIBUTES                   DimmModuleAttributes;        
  SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION      ThermalHeatSpreaderSolution; 
  SPD3_MANUFACTURER_ID_CODE                      RegisterManufacturerIdCode;  
  SPD3_RDIMM_REGISTER_REVISION_NUMBER            RegisterRevisionNumber;      
  SPD3_RDIMM_REGISTER_TYPE                       RegisterType;                
  SPD3_RDIMM_REGISTER_CONTROL_RESERVED           Rc1Rc0;                      
  SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS    Rc3Rc2;                      
  SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK      Rc5Rc4;                      
  SPD3_RDIMM_REGISTER_CONTROL_RESERVED           Rc7Rc6;                      
  SPD3_RDIMM_REGISTER_CONTROL_RESERVED           Rc9Rc8;                      
  SPD3_RDIMM_REGISTER_CONTROL_RESERVED           Rc11Rc10;                    
  SPD3_RDIMM_REGISTER_CONTROL_RESERVED           Rc13Rc12;                    
  SPD3_RDIMM_REGISTER_CONTROL_RESERVED           Rc15Rc14;                    
  UINT8                                          Reserved[116 - 77 + 1];      
} SPD3_MODULE_REGISTERED;
 
typedef struct {
  SPD3_UNBUF_MODULE_NOMINAL_HEIGHT       ModuleNominalHeight;    
  SPD3_UNBUF_MODULE_NOMINAL_THICKNESS    ModuleMaximumThickness; 
  SPD3_UNBUF_REFERENCE_RAW_CARD          ReferenceRawCardUsed;   
  UINT8                                  Reserved[116 - 63 + 1]; 
} SPD3_MODULE_CLOCKED;
 
typedef struct {
  SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT             ModuleNominalHeight;                     
  SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS          ModuleMaximumThickness;                  
  SPD3_LRDIMM_REFERENCE_RAW_CARD                ReferenceRawCardUsed;                    
  SPD3_LRDIMM_MODULE_ATTRIBUTES                 DimmModuleAttributes;                    
  UINT8                                         MemoryBufferRevisionNumber;              
  SPD3_MANUFACTURER_ID_CODE                     ManufacturerIdCode;                      
  SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH     TimingControlDriveStrengthCaCs;          
  SPD3_LRDIMM_TIMING_DRIVE_STRENGTH             DriveStrength;                           
  SPD3_LRDIMM_EXTENDED_DELAY                    ExtendedDelay;                           
  SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA    AdditiveDelayForCsCa;                    
  SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE    AdditiveDelayForOdtCke;                  
  SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor800_1066;  
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor800_1066;         
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor800_1066;         
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor800_1066;         
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor800_1066;         
  SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor800_1066;              
  SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor1333_1600; 
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor1333_1600;        
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor1333_1600;        
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor1333_1600;        
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor1333_1600;        
  SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor1333_1600;             
  SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH    MdqTerminationDriveStrengthFor1866_2133; 
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_0_1QxOdtControlFor1866_2133;        
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_2_3QxOdtControlFor1866_2133;        
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_4_5QxOdtControlFor1866_2133;        
  SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL     Rank_6_7QxOdtControlFor1866_2133;        
  SPD3_LRDIMM_MR_1_2                            MR_1_2RegistersFor1866_2133;             
  SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_5V;           
  SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_5V;           
  SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_35V;          
  SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_35V;          
  SPD3_LRDIMM_MODULE_DELAY_TIME                 MinimumModuleDelayTimeFor1_25V;          
  SPD3_LRDIMM_MODULE_DELAY_TIME                 MaximumModuleDelayTimeFor1_25V;          
  UINT8                                         Reserved[101 - 96 + 1];                  
  UINT8                                         PersonalityByte[116 - 102 + 1];          
} SPD3_MODULE_LOADREDUCED;
 
typedef union {
  SPD3_MODULE_UNBUFFERED     Unbuffered;                        
  SPD3_MODULE_REGISTERED     Registered;                        
  SPD3_MODULE_CLOCKED        Clocked;                           
  SPD3_MODULE_LOADREDUCED    LoadReduced;                       
} SPD3_MODULE_SPECIFIC;
 
typedef struct {
  UINT8    ModulePartNumber[145 - 128 + 1];                              
} SPD3_MODULE_PART_NUMBER;
 
typedef struct {
  UINT8    ModuleRevisionCode[147 - 146 + 1];                            
} SPD3_MODULE_REVISION_CODE;
 
typedef struct {
  UINT8    ManufacturerSpecificData[175 - 150 + 1];                      
} SPD3_MANUFACTURER_SPECIFIC;
 
typedef struct {
  SPD3_BASE_SECTION              General;                             
  SPD3_MODULE_SPECIFIC           Module;                              
  SPD3_UNIQUE_MODULE_ID          ModuleId;                            
  SPD3_CYCLIC_REDUNDANCY_CODE    Crc;                                 
  SPD3_MODULE_PART_NUMBER        ModulePartNumber;                    
  SPD3_MODULE_REVISION_CODE      ModuleRevisionCode;                  
  SPD3_MANUFACTURER_ID_CODE      DramIdCode;                          
  SPD3_MANUFACTURER_SPECIFIC     ManufacturerSpecificData;            
  UINT8                          Reserved[255 - 176 + 1];             
} SPD_DDR3;
 
#pragma pack (pop)
#endif