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SdramSpdLpDdr.h
Go to the documentation of this file.
1
12#ifndef _SDRAM_SPD_LPDDR_H_
13#define _SDRAM_SPD_LPDDR_H_
14
15#pragma pack (push, 1)
16
17typedef union {
18 struct {
19 UINT8 BytesUsed : 4;
20 UINT8 BytesTotal : 3;
21 UINT8 CrcCoverage : 1;
22 } Bits;
23 UINT8 Data;
25
26typedef union {
27 struct {
28 UINT8 Minor : 4;
29 UINT8 Major : 4;
30 } Bits;
31 UINT8 Data;
33
34typedef union {
35 struct {
36 UINT8 Type : 8;
37 } Bits;
38 UINT8 Data;
40
41typedef union {
42 struct {
43 UINT8 ModuleType : 4;
44 UINT8 HybridMedia : 3;
45 UINT8 Hybrid : 1;
46 } Bits;
47 UINT8 Data;
49
50typedef union {
51 struct {
52 UINT8 Density : 4;
53 UINT8 BankAddress : 2;
54 UINT8 BankGroup : 2;
55 } Bits;
56 UINT8 Data;
58
59typedef union {
60 struct {
61 UINT8 ColumnAddress : 3;
62 UINT8 RowAddress : 3;
63 UINT8 Reserved : 2;
64 } Bits;
65 UINT8 Data;
67
68typedef union {
69 struct {
70 UINT8 SignalLoading : 2;
71 UINT8 ChannelsPerDie : 2;
72 UINT8 DieCount : 3;
73 UINT8 SdramPackageType : 1;
74 } Bits;
75 UINT8 Data;
77
78typedef union {
79 struct {
82 UINT8 Reserved : 2;
83 } Bits;
84 UINT8 Data;
86
87typedef union {
88 struct {
89 UINT8 Reserved : 8;
90 } Bits;
91 UINT8 Data;
93
94typedef union {
95 struct {
96 UINT8 Reserved : 5;
97 UINT8 SoftPPR : 1;
99 } Bits;
100 UINT8 Data;
102
103typedef union {
104 struct {
105 UINT8 OperationAt1_20 : 1;
106 UINT8 EndurantAt1_20 : 1;
107 UINT8 OperationAt1_10 : 1;
108 UINT8 EndurantAt1_10 : 1;
110 UINT8 EndurantAtTBD2V : 1;
111 UINT8 Reserved : 2;
112 } Bits;
113 UINT8 Data;
115
116typedef union {
117 struct {
119 UINT8 RankCount : 3;
120 UINT8 Reserved : 2;
121 } Bits;
122 UINT8 Data;
124
125typedef union {
126 struct {
127 UINT8 PrimaryBusWidth : 3;
130 } Bits;
131 UINT8 Data;
133
134typedef union {
135 struct {
136 UINT8 Reserved : 7;
138 } Bits;
139 UINT8 Data;
141
142typedef union {
143 struct {
145 UINT8 Reserved : 4;
146 } Bits;
147 UINT8 Data;
149
150typedef union {
151 struct {
155 } Bits;
156 UINT8 Data;
158
159typedef union {
160 struct {
161 UINT8 Fine : 2;
162 UINT8 Medium : 2;
163 UINT8 Reserved : 4;
164 } Bits;
165 UINT8 Data;
167
168typedef union {
169 struct {
170 UINT8 tCKmin : 8;
171 } Bits;
172 UINT8 Data;
174
175typedef union {
176 struct {
177 UINT8 tCKmax : 8;
178 } Bits;
179 UINT8 Data;
181
182typedef union {
183 struct {
184 UINT32 Cl3 : 1;
185 UINT32 Cl6 : 1;
186 UINT32 Cl8 : 1;
187 UINT32 Cl9 : 1;
188 UINT32 Cl10 : 1;
189 UINT32 Cl11 : 1;
190 UINT32 Cl12 : 1;
191 UINT32 Cl14 : 1;
192 UINT32 Cl16 : 1;
193 UINT32 Reserved0 : 1;
194 UINT32 Cl20 : 1;
195 UINT32 Cl22 : 1;
196 UINT32 Cl24 : 1;
197 UINT32 Reserved1 : 1;
198 UINT32 Cl28 : 1;
199 UINT32 Reserved2 : 1;
200 UINT32 Cl32 : 1;
201 UINT32 Reserved3 : 1;
202 UINT32 Cl36 : 1;
203 UINT32 Reserved4 : 1;
204 UINT32 Cl40 : 1;
205 UINT32 Reserved5 : 11;
206 } Bits;
207 UINT32 Data;
208 UINT16 Data16[2];
209 UINT8 Data8[4];
211
212typedef union {
213 struct {
214 UINT8 tAAmin : 8;
215 } Bits;
216 UINT8 Data;
218
219typedef union {
220 struct {
221 UINT8 ReadLatencyMode : 2;
222 UINT8 WriteLatencySet : 2;
223 UINT8 Reserved : 4;
224 } Bits;
225 UINT8 Data;
227
228typedef union {
229 struct {
230 UINT8 tRCDmin : 8;
231 } Bits;
232 UINT8 Data;
234
235typedef union {
236 struct {
237 UINT8 tRPab : 8;
238 } Bits;
239 UINT8 Data;
241
242typedef union {
243 struct {
244 UINT8 tRPpb : 8;
245 } Bits;
246 UINT8 Data;
248
249typedef union {
250 struct {
251 UINT16 tRFCab : 16;
252 } Bits;
253 UINT16 Data;
254 UINT8 Data8[2];
256
257typedef union {
258 struct {
259 UINT16 tRFCpb : 16;
260 } Bits;
261 UINT16 Data;
262 UINT8 Data8[2];
264
265typedef union {
266 struct {
267 UINT8 BitOrderatSDRAM : 5;
269 UINT8 PackageRankMap : 2;
270 } Bits;
271 UINT8 Data;
273
274typedef union {
275 struct {
276 INT8 tRPpbFine : 8;
277 } Bits;
278 INT8 Data;
280
281typedef union {
282 struct {
283 INT8 tRPabFine : 8;
284 } Bits;
285 INT8 Data;
287
288typedef union {
289 struct {
290 INT8 tRCDminFine : 8;
291 } Bits;
292 INT8 Data;
294
295typedef union {
296 struct {
297 INT8 tAAminFine : 8;
298 } Bits;
299 INT8 Data;
301
302typedef union {
303 struct {
304 INT8 tCKmaxFine : 8;
305 } Bits;
306 INT8 Data;
308
309typedef union {
310 struct {
311 INT8 tCKminFine : 8;
312 } Bits;
313 INT8 Data;
315
316typedef union {
317 struct {
318 UINT16 ContinuationCount : 7;
320 UINT16 LastNonZeroByte : 8;
321 } Bits;
322 UINT16 Data;
323 UINT8 Data8[2];
325
326typedef struct {
327 UINT8 Location;
329
330typedef struct {
331 UINT8 Year;
332 UINT8 Week;
334
335typedef union {
336 UINT32 Data;
337 UINT16 SerialNumber16[2];
338 UINT8 SerialNumber8[4];
340
341typedef struct {
347
348typedef union {
349 struct {
350 UINT8 FrontThickness : 4;
351 UINT8 BackThickness : 4;
352 } Bits;
353 UINT8 Data;
355
356typedef union {
357 struct {
358 UINT8 Height : 5;
360 } Bits;
361 UINT8 Data;
363
364typedef union {
365 struct {
366 UINT8 Card : 5;
367 UINT8 Revision : 2;
368 UINT8 Extension : 1;
369 } Bits;
370 UINT8 Data;
372
373typedef union {
374 UINT16 Crc[1];
375 UINT8 Data8[2];
377
378typedef struct {
389 UINT8 Reserved0;
407 UINT8 Reserved1[59 - 33 + 1];
409 UINT8 Reserved2[119 - 78 + 1];
418
419typedef struct {
423 UINT8 Reserved[253 - 131 + 1];
426
427typedef struct {
430
431typedef struct {
432 UINT8 ModulePartNumber[348 - 329 + 1];
434
435typedef struct {
436 UINT8 ManufacturerSpecificData[381 - 353 + 1];
438
441
442typedef struct {
449 UINT8 Reserved[383 - 382 + 1];
451
452typedef struct {
453 UINT8 Reserved[511 - 384 + 1];
455
459typedef struct {
462 UINT8 Reserved[319 - 256 + 1];
465} SPD_LPDDR;
466
467#pragma pack (pop)
468#endif
UINT8 SPD_LPDDR_MODULE_REVISION_CODE
349 Module Revision Code
UINT8 SPD_LPDDR_DRAM_STEPPING
352 Dram Stepping
SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures
9 Other SDRAM Optional Features
SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading
16 Signal Loading
SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin
26 Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_REVISION_STRUCT Revision
1 SPD Revision
SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax
19 SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions
25 Read and Write Latency Set Options
SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin
18 SDRAM Minimum Cycle Time (tCKmin)
UINT8 Reserved0
10 Reserved
SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin
24 Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType
2 DRAM Device Type
SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb
28 Minimum Row Precharge Delay Time (tRPpb), per bank
SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType
3 Module Type
SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description
0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures
7 SDRAM Optional Features
SPD_LPDDR_TIMEBASE_STRUCT Timebase
17 Timebases
SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine
122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies
20-23 CAS Latencies Supported
SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType
6 SDRAM Package Type
SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization
12 Module Organization
SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth
13 Module Memory Bus Width
SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine
123 Fine Offset for Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine
120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine
121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions
8 SDRAM Thermal and Refresh Options
SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType
15 Extended Module Type
SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine
125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks
4 SDRAM Density and Banks
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
126-127 Cyclical Redundancy Code (CRC)
SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb
31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine
124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage
11 Module Nominal Voltage, VDD
SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab
27 Minimum Row Precharge Delay Time (tRPab), all banks
SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing
5 SDRAM Addressing
SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab
29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor
14 Module Thermal Sensor
SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode
350-351 Dram Manufacturer ID Code
SPD_LPDDR_UNIQUE_MODULE_ID ModuleId
320-328 Unique Module ID
SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData
353-381 Manufacturer's Specific Data
SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber
329-348 Module Part Number
SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode
349 Module Revision Code
SPD_LPDDR_DRAM_STEPPING DramStepping
352 Dram Stepping
UINT8 Week
Year represented in BCD (47h = week 47)
UINT8 Year
Year represented in BCD (00h = 2000)
UINT8 Location
Module Manufacturing Location.
SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness
129 Module Maximum Thickness
SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
128 Module Nominal Height
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
254-255 Cyclical Redundancy Code (CRC)
SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed
130 Reference Raw Card Used
SPD_LPDDR_MODULE_LPDIMM LpDimm
128-255 Unbuffered Memory Module Types
SPD_LPDDR_MANUFACTURING_DATE Date
Module Manufacturing Year, in BCD (range: 2000-2255)
SPD_LPDDR_MANUFACTURER_ID_CODE IdCode
Module Manufacturer ID Code.
SPD_LPDDR_MANUFACTURING_LOCATION Location
Module Manufacturing Location.
SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber
Module Serial Number.
SPD_LPDDR_BASE_SECTION Base
0-127 Base Configuration and DRAM Parameters
SPD_LPDDR_MODULE_SPECIFIC Module
128-255 Module-Specific Section
SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo
320-383 Manufacturing Information
SPD_LPDDR_END_USER_SECTION EndUser
384-511 End User Programmable
UINT16 LastNonZeroByte
Bits 15:8.
UINT16 ContinuationParity
Bits 7:7.
UINT8 CommandAddressControlClockLoading
Bits 5:3.