12#ifndef _SDRAM_SPD_LPDDR_H_
13#define _SDRAM_SPD_LPDDR_H_
337 UINT16 SerialNumber16[2];
338 UINT8 SerialNumber8[4];
407 UINT8 Reserved1[59 - 33 + 1];
409 UINT8 Reserved2[119 - 78 + 1];
423 UINT8 Reserved[253 - 131 + 1];
432 UINT8 ModulePartNumber[348 - 329 + 1];
436 UINT8 ManufacturerSpecificData[381 - 353 + 1];
449 UINT8 Reserved[383 - 382 + 1];
453 UINT8 Reserved[511 - 384 + 1];
462 UINT8 Reserved[319 - 256 + 1];
UINT8 SPD_LPDDR_MODULE_REVISION_CODE
349 Module Revision Code
UINT8 SPD_LPDDR_DRAM_STEPPING
352 Dram Stepping
SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures
9 Other SDRAM Optional Features
SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading
16 Signal Loading
SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin
26 Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_REVISION_STRUCT Revision
1 SPD Revision
SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax
19 SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions
25 Read and Write Latency Set Options
SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin
18 SDRAM Minimum Cycle Time (tCKmin)
UINT8 Reserved0
10 Reserved
SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin
24 Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType
2 DRAM Device Type
SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb
28 Minimum Row Precharge Delay Time (tRPpb), per bank
SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType
3 Module Type
SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description
0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures
7 SDRAM Optional Features
SPD_LPDDR_TIMEBASE_STRUCT Timebase
17 Timebases
SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine
122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies
20-23 CAS Latencies Supported
SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType
6 SDRAM Package Type
SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization
12 Module Organization
SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth
13 Module Memory Bus Width
SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine
123 Fine Offset for Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine
120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine
121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions
8 SDRAM Thermal and Refresh Options
SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType
15 Extended Module Type
SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine
125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks
4 SDRAM Density and Banks
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
126-127 Cyclical Redundancy Code (CRC)
SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb
31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine
124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage
11 Module Nominal Voltage, VDD
SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab
27 Minimum Row Precharge Delay Time (tRPab), all banks
SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing
5 SDRAM Addressing
SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab
29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor
14 Module Thermal Sensor
SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode
350-351 Dram Manufacturer ID Code
SPD_LPDDR_UNIQUE_MODULE_ID ModuleId
320-328 Unique Module ID
SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData
353-381 Manufacturer's Specific Data
SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber
329-348 Module Part Number
SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode
349 Module Revision Code
SPD_LPDDR_DRAM_STEPPING DramStepping
352 Dram Stepping
UINT8 Week
Year represented in BCD (47h = week 47)
UINT8 Year
Year represented in BCD (00h = 2000)
UINT8 Location
Module Manufacturing Location.
SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness
129 Module Maximum Thickness
SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
128 Module Nominal Height
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc
254-255 Cyclical Redundancy Code (CRC)
SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed
130 Reference Raw Card Used
SPD_LPDDR_MODULE_LPDIMM LpDimm
128-255 Unbuffered Memory Module Types
SPD_LPDDR_MANUFACTURING_DATE Date
Module Manufacturing Year, in BCD (range: 2000-2255)
SPD_LPDDR_MANUFACTURER_ID_CODE IdCode
Module Manufacturer ID Code.
SPD_LPDDR_MANUFACTURING_LOCATION Location
Module Manufacturing Location.
SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber
Module Serial Number.
SPD_LPDDR_BASE_SECTION Base
0-127 Base Configuration and DRAM Parameters
SPD_LPDDR_MODULE_SPECIFIC Module
128-255 Module-Specific Section
SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo
320-383 Manufacturing Information
SPD_LPDDR_END_USER_SECTION EndUser
384-511 End User Programmable
UINT32 Reserved2
Bits 15:15.
UINT32 Reserved0
Bits 9:9.
UINT32 Reserved3
Bits 17:17.
UINT32 Reserved4
Bits 19:19.
UINT32 Reserved5
Bits 31:21.
UINT32 Reserved1
Bits 13:13.
UINT8 WiredtoUpperLowerNibble
Bits 5:5.
UINT8 PackageRankMap
Bits 7:6.
UINT8 BitOrderatSDRAM
Bits 4:0.
UINT8 BytesTotal
Bits 6:4.
UINT8 CrcCoverage
Bits 7:7.
UINT8 ExtendedBaseModuleType
Bits 3:0.
UINT16 ContinuationCount
Bits 6:0.
UINT16 LastNonZeroByte
Bits 15:8.
UINT16 ContinuationParity
Bits 7:7.
UINT8 FrontThickness
Bits 3:0.
UINT8 BackThickness
Bits 7:4.
UINT8 BusWidthExtension
Bits 4:3.
UINT8 PrimaryBusWidth
Bits 2:0.
UINT8 NumberofChannels
Bits 7:5.
UINT8 RawCardExtension
Bits 7:5.
UINT8 EndurantAt1_20
Bits 1:1.
UINT8 EndurantAt1_10
Bits 3:3.
UINT8 OperationAtTBD2V
Bits 4:4.
UINT8 OperationAt1_20
Bits 0:0.
UINT8 EndurantAtTBD2V
Bits 5:5.
UINT8 OperationAt1_10
Bits 2:2.
UINT8 SdramDeviceWidth
Bits 2:0.
UINT8 ThermalSensorPresence
Bits 7:7.
UINT8 HybridMedia
Bits 6:4.
UINT8 ModuleType
Bits 3:0.
UINT8 PostPackageRepair
Bits 7:6.
UINT8 WriteLatencySet
Bits 3:2.
UINT8 ReadLatencyMode
Bits 1:0.
UINT8 RowAddress
Bits 5:3.
UINT8 ColumnAddress
Bits 2:0.
UINT8 BankAddress
Bits 5:4.
UINT8 MaximumActivateWindow
Bits 5:4.
UINT8 MaximumActivateCount
Bits 3:0.
UINT8 SdramPackageType
Bits 7:7.
UINT8 SignalLoading
Bits 1:0.
UINT8 ChannelsPerDie
Bits 3:2.
UINT8 CommandAddressControlClockLoading
Bits 5:3.
UINT8 DataStrobeMaskLoading
Bits 7:6.
UINT8 ChipSelectLoading
Bits 2:0.
INT8 tRCDminFine
Bits 7:0.