TpmCommLib.h

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#ifndef _TPM_COMM_LIB_H_
#define _TPM_COMM_LIB_H_
 
#include <IndustryStandard/Tpm12.h>
 
typedef EFI_HANDLE TIS_TPM_HANDLE;
 
#define TPM_BASE_ADDRESS  0xfed40000
 
//
// Set structure alignment to 1-byte
//
#pragma pack (1)
 
//
// Register set map as specified in TIS specification Chapter 10
//
typedef struct {
  UINT8     Access;                                     // 0
  UINT8     Reserved1[7];                               // 1
  UINT32    IntEnable;                                  // 8
  UINT8     IntVector;                                  // 0ch
  UINT8     Reserved2[3];                               // 0dh
  UINT32    IntSts;                                     // 10h
  UINT32    IntfCapability;                             // 14h
  UINT8     Status;                                     // 18h
  UINT16    BurstCount;                                 // 19h
  UINT8     Reserved3[9];
  UINT32    DataFifo;                                   // 24
  UINT8     Reserved4[0xed8];                           // 28h
  UINT16    Vid;                                        // 0f00h
  UINT16    Did;                                        // 0f02h
  UINT8     Rid;                                        // 0f04h
  UINT8     TcgDefined[0x7b];                           // 0f05h
  UINT32    LegacyAddress1;                             // 0f80h
  UINT32    LegacyAddress1Ex;                           // 0f84h
  UINT32    LegacyAddress2;                             // 0f88h
  UINT32    LegacyAddress2Ex;                           // 0f8ch
  UINT8     VendorDefined[0x70];                        // 0f90h
} TIS_PC_REGISTERS;
 
//
// Restore original structure alignment
//
#pragma pack ()
 
//
// Define pointer types used to access TIS registers on PC
//
typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
 
//
// TCG Platform Type based on TCG ACPI Specification Version 1.00
//
#define TCG_PLATFORM_TYPE_CLIENT  0
#define TCG_PLATFORM_TYPE_SERVER  1
 
//
// Define bits of ACCESS and STATUS registers
//
 
#define TIS_PC_VALID  BIT7
#define TIS_PC_ACC_ACTIVE  BIT5
#define TIS_PC_ACC_SEIZED  BIT4
#define TIS_PC_ACC_SEIZE  BIT3
#define TIS_PC_ACC_PENDIND  BIT2
#define TIS_PC_ACC_RQUUSE  BIT1
#define TIS_PC_ACC_ESTABLISH  BIT0
 
#define TIS_PC_STS_READY  BIT6
#define TIS_PC_STS_GO  BIT5
#define TIS_PC_STS_DATA  BIT4
#define TIS_PC_STS_EXPECT  BIT3
#define TIS_PC_STS_RETRY  BIT1
 
//
// Default TimeOut value
//
#define TIS_TIMEOUT_A  750 * 1000                // 750ms
#define TIS_TIMEOUT_B  2000 * 1000               // 2s
#define TIS_TIMEOUT_C  750 * 1000                // 750ms
#define TIS_TIMEOUT_D  750 * 1000                // 750ms
 
//
// Max TPM command/response length
//
#define TPMCMDBUFLENGTH  1024
 
EFI_STATUS
EFIAPI
TisPcWaitRegisterBits (
  IN UINT8   *Register,
  IN UINT8   BitSet,
  IN UINT8   BitClear,
  IN UINT32  TimeOut
  );
 
EFI_STATUS
EFIAPI
TisPcReadBurstCount (
  IN  TIS_PC_REGISTERS_PTR  TisReg,
  OUT UINT16                *BurstCount
  );
 
EFI_STATUS
EFIAPI
TisPcPrepareCommand (
  IN TIS_PC_REGISTERS_PTR  TisReg
  );
 
EFI_STATUS
EFIAPI
TisPcRequestUseTpm (
  IN TIS_PC_REGISTERS_PTR  TisReg
  );
 
EFI_STATUS
EFIAPI
TpmCommHashAll (
  IN  CONST UINT8       *Data,
  IN        UINTN       DataLen,
  OUT       TPM_DIGEST  *Digest
  );
 
#endif