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TpmTis.h
Go to the documentation of this file.
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#ifndef _TPM_TIS_H_
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#define _TPM_TIS_H_
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//
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// Set structure alignment to 1-byte
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//
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#pragma pack (1)
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//
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// Register set map as specified in TIS specification Chapter 10
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//
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typedef
struct
{
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UINT8
Access
;
// 0
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UINT8 Reserved1[7];
// 1
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UINT32
IntEnable
;
// 8
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UINT8
IntVector
;
// 0ch
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UINT8 Reserved2[3];
// 0dh
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UINT32
IntSts
;
// 10h
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UINT32
IntfCapability
;
// 14h
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UINT8
Status
;
// 18h
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UINT16
BurstCount
;
// 19h
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UINT8 Reserved3[9];
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UINT32
DataFifo
;
// 24h
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UINT8 Reserved4[0xed8];
// 28h
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UINT16
Vid
;
// 0f00h
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UINT16
Did
;
// 0f02h
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UINT8
Rid
;
// 0f04h
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UINT8 Reserved[0x7b];
// 0f05h
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UINT32
LegacyAddress1
;
// 0f80h
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UINT32
LegacyAddress1Ex
;
// 0f84h
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UINT32
LegacyAddress2
;
// 0f88h
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UINT32
LegacyAddress2Ex
;
// 0f8ch
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UINT8 VendorDefined[0x70];
// 0f90h
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}
TIS_PC_REGISTERS
;
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//
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// Restore original structure alignment
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//
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#pragma pack ()
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//
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// Define pointer types used to access TIS registers on PC
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//
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typedef
TIS_PC_REGISTERS
*
TIS_PC_REGISTERS_PTR
;
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//
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// Define bits of ACCESS and STATUS registers
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//
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#define TIS_PC_VALID BIT7
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#define TIS_PC_ACC_ACTIVE BIT5
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#define TIS_PC_ACC_SEIZED BIT4
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#define TIS_PC_ACC_SEIZE BIT3
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#define TIS_PC_ACC_PENDIND BIT2
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#define TIS_PC_ACC_RQUUSE BIT1
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#define TIS_PC_ACC_ESTABLISH BIT0
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#define TIS_PC_STS_CANCEL BIT24
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#define TIS_PC_STS_VALID BIT7
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#define TIS_PC_STS_READY BIT6
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#define TIS_PC_STS_GO BIT5
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#define TIS_PC_STS_DATA BIT4
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#define TIS_PC_STS_EXPECT BIT3
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#define TIS_PC_STS_SELFTEST_DONE BIT2
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#define TIS_PC_STS_RETRY BIT1
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//
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// Default TimeOut value
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//
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#define TIS_TIMEOUT_A (750 * 1000)
// 750ms
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#define TIS_TIMEOUT_B (2000 * 1000)
// 2s
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#define TIS_TIMEOUT_C (750 * 1000)
// 750ms
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#define TIS_TIMEOUT_D (750 * 1000)
// 750ms
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#endif
TIS_PC_REGISTERS
Definition:
TpmTis.h:21
TIS_PC_REGISTERS::Vid
UINT16 Vid
Definition:
TpmTis.h:61
TIS_PC_REGISTERS::Did
UINT16 Did
Definition:
TpmTis.h:65
TIS_PC_REGISTERS::Access
UINT8 Access
Definition:
TpmTis.h:25
TIS_PC_REGISTERS::IntfCapability
UINT32 IntfCapability
Definition:
TpmTis.h:43
TIS_PC_REGISTERS::LegacyAddress2Ex
UINT32 LegacyAddress2Ex
Definition:
TpmTis.h:86
TIS_PC_REGISTERS::Status
UINT8 Status
Definition:
TpmTis.h:47
TIS_PC_REGISTERS::IntVector
UINT8 IntVector
Definition:
TpmTis.h:34
TIS_PC_REGISTERS::DataFifo
UINT32 DataFifo
Definition:
TpmTis.h:56
TIS_PC_REGISTERS::IntEnable
UINT32 IntEnable
Definition:
TpmTis.h:30
TIS_PC_REGISTERS::BurstCount
UINT16 BurstCount
Definition:
TpmTis.h:51
TIS_PC_REGISTERS::LegacyAddress1
UINT32 LegacyAddress1
Definition:
TpmTis.h:74
TIS_PC_REGISTERS::Rid
UINT8 Rid
Definition:
TpmTis.h:69
TIS_PC_REGISTERS::IntSts
UINT32 IntSts
Definition:
TpmTis.h:39
TIS_PC_REGISTERS::LegacyAddress1Ex
UINT32 LegacyAddress1Ex
Definition:
TpmTis.h:78
TIS_PC_REGISTERS::LegacyAddress2
UINT32 LegacyAddress2
Definition:
TpmTis.h:82
MdePkg
Include
IndustryStandard
TpmTis.h
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