#include "BaseLibInternals.h"
#include <Library/RegisterFilterLib.h>

Functions
VOID EFIAPI	EnableInterrupts (VOID)

VOID EFIAPI	DisableInterrupts (VOID)

UINT64 EFIAPI	AsmReadMsr64 (IN UINT32 Index)

UINT64 EFIAPI	AsmWriteMsr64 (IN UINT32 Index, IN UINT64 Value)

UINTN EFIAPI	AsmReadCr0 (VOID)

UINTN EFIAPI	AsmReadCr2 (VOID)

UINTN EFIAPI	AsmReadCr3 (VOID)

UINTN EFIAPI	AsmReadCr4 (VOID)

UINTN EFIAPI	AsmWriteCr0 (UINTN Cr0)

UINTN EFIAPI	AsmWriteCr2 (UINTN Cr2)

UINTN EFIAPI	AsmWriteCr3 (UINTN Cr3)

UINTN EFIAPI	AsmWriteCr4 (UINTN Cr4)

UINTN EFIAPI	AsmReadDr0 (VOID)

UINTN EFIAPI	AsmReadDr1 (VOID)

UINTN EFIAPI	AsmReadDr2 (VOID)

UINTN EFIAPI	AsmReadDr3 (VOID)

UINTN EFIAPI	AsmReadDr4 (VOID)

UINTN EFIAPI	AsmReadDr5 (VOID)

UINTN EFIAPI	AsmReadDr6 (VOID)

UINTN EFIAPI	AsmReadDr7 (VOID)

UINTN EFIAPI	AsmWriteDr0 (UINTN Dr0)

UINTN EFIAPI	AsmWriteDr1 (UINTN Dr1)

UINTN EFIAPI	AsmWriteDr2 (UINTN Dr2)

UINTN EFIAPI	AsmWriteDr3 (UINTN Dr3)

UINTN EFIAPI	AsmWriteDr4 (UINTN Dr4)

UINTN EFIAPI	AsmWriteDr5 (UINTN Dr5)

UINTN EFIAPI	AsmWriteDr6 (UINTN Dr6)

UINTN EFIAPI	AsmWriteDr7 (UINTN Dr7)

UINT16 EFIAPI	AsmReadCs (VOID)

UINT16 EFIAPI	AsmReadDs (VOID)

UINT16 EFIAPI	AsmReadEs (VOID)

UINT16 EFIAPI	AsmReadFs (VOID)

UINT16 EFIAPI	AsmReadGs (VOID)

UINT16 EFIAPI	AsmReadSs (VOID)

UINT16 EFIAPI	AsmReadTr (VOID)

VOID EFIAPI	InternalX86ReadGdtr (OUT IA32_DESCRIPTOR *Gdtr)

VOID EFIAPI	InternalX86WriteGdtr (IN CONST IA32_DESCRIPTOR *Gdtr)

VOID EFIAPI	InternalX86ReadIdtr (OUT IA32_DESCRIPTOR *Idtr)

VOID EFIAPI	InternalX86WriteIdtr (IN CONST IA32_DESCRIPTOR *Idtr)

UINT16 EFIAPI	AsmReadLdtr (VOID)

VOID EFIAPI	AsmWriteLdtr (IN UINT16 Ldtr)

UINT64 EFIAPI	AsmReadPmc (IN UINT32 Index)

UINTN EFIAPI	AsmMonitor (IN UINTN Eax, IN UINTN Ecx, IN UINTN Edx)

UINTN EFIAPI	AsmMwait (IN UINTN Eax, IN UINTN Ecx)

VOID EFIAPI	AsmWbinvd (VOID)

VOID EFIAPI	AsmInvd (VOID)

VOID *EFIAPI	AsmFlushCacheLine (IN VOID *LinearAddress)

Detailed Description

GCC inline implementation of BaseLib processor specific functions that use privlidged instructions.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file GccInlinePriv.c.

Function Documentation

◆ AsmFlushCacheLine()

VOID *EFIAPI AsmFlushCacheLine ( IN VOID * LinearAddress )

Flushes a cache line from all the instruction and data caches within the coherency domain of the CPU.

Flushed the cache line specified by LinearAddress, and returns LinearAddress. This function is only available on IA-32 and X64.

Parameters

LinearAddress The address of the cache line to flush. If the CPU is in a physical addressing mode, then LinearAddress is a physical address. If the CPU is in a virtual addressing mode, then LinearAddress is a virtual address.

Returns: LinearAddress

Definition at line 1196 of file GccInlinePriv.c.

◆ AsmInvd()

VOID EFIAPI AsmInvd ( VOID )

Executes a INVD instruction.

Executes a INVD instruction. This function is only available on IA-32 and X64.

Definition at line 1172 of file GccInlinePriv.c.

◆ AsmMonitor()

UINTN EFIAPI AsmMonitor	(	IN UINTN	Eax,
		IN UINTN	Ecx,
		IN UINTN	Edx
	)

Sets up a monitor buffer that is used by AsmMwait().

Executes a MONITOR instruction with the register state specified by Eax, Ecx and Edx. Returns Eax. This function is only available on IA-32 and X64.

Parameters

Eax	The value to load into EAX or RAX before executing the MONITOR instruction.
Ecx	The value to load into ECX or RCX before executing the MONITOR instruction.
Edx	The value to load into EDX or RDX before executing the MONITOR instruction.

Returns: Eax

Definition at line 1099 of file GccInlinePriv.c.

◆ AsmMwait()

UINTN EFIAPI AsmMwait	(	IN UINTN	Eax,
		IN UINTN	Ecx
	)

Executes an MWAIT instruction.

Executes an MWAIT instruction with the register state specified by Eax and Ecx. Returns Eax. This function is only available on IA-32 and X64.

Parameters

Eax	The value to load into EAX or RAX before executing the MONITOR instruction.
Ecx	The value to load into ECX or RCX before executing the MONITOR instruction.

Returns: Eax

Definition at line 1132 of file GccInlinePriv.c.

◆ AsmReadCr0()

UINTN EFIAPI AsmReadCr0 ( VOID )

Reads the current value of the Control Register 0 (CR0).

Reads and returns the current value of CR0. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of the Control Register 0 (CR0).

Definition at line 143 of file GccInlinePriv.c.

◆ AsmReadCr2()

UINTN EFIAPI AsmReadCr2 ( VOID )

Reads the current value of the Control Register 2 (CR2).

Reads and returns the current value of CR2. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of the Control Register 2 (CR2).

Definition at line 169 of file GccInlinePriv.c.

◆ AsmReadCr3()

UINTN EFIAPI AsmReadCr3 ( VOID )

Reads the current value of the Control Register 3 (CR3).

Reads and returns the current value of CR3. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of the Control Register 3 (CR3).

Definition at line 195 of file GccInlinePriv.c.

◆ AsmReadCr4()

UINTN EFIAPI AsmReadCr4 ( VOID )

Reads the current value of the Control Register 4 (CR4).

Reads and returns the current value of CR4. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of the Control Register 4 (CR4).

Definition at line 221 of file GccInlinePriv.c.

◆ AsmReadCs()

UINT16 EFIAPI AsmReadCs ( VOID )

Reads the current value of Code Segment Register (CS).

Reads and returns the current value of CS. This function is only available on IA-32 and X64.

Returns: The current value of CS.

Definition at line 754 of file GccInlinePriv.c.

◆ AsmReadDr0()

UINTN EFIAPI AsmReadDr0 ( VOID )

Reads the current value of Debug Register 0 (DR0).

Reads and returns the current value of DR0. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 0 (DR0).

Definition at line 347 of file GccInlinePriv.c.

◆ AsmReadDr1()

UINTN EFIAPI AsmReadDr1 ( VOID )

Reads the current value of Debug Register 1 (DR1).

Reads and returns the current value of DR1. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 1 (DR1).

Definition at line 373 of file GccInlinePriv.c.

◆ AsmReadDr2()

UINTN EFIAPI AsmReadDr2 ( VOID )

Reads the current value of Debug Register 2 (DR2).

Reads and returns the current value of DR2. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 2 (DR2).

Definition at line 399 of file GccInlinePriv.c.

◆ AsmReadDr3()

UINTN EFIAPI AsmReadDr3 ( VOID )

Reads the current value of Debug Register 3 (DR3).

Reads and returns the current value of DR3. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 3 (DR3).

Definition at line 425 of file GccInlinePriv.c.

◆ AsmReadDr4()

UINTN EFIAPI AsmReadDr4 ( VOID )

Reads the current value of Debug Register 4 (DR4).

Reads and returns the current value of DR4. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 4 (DR4).

Definition at line 451 of file GccInlinePriv.c.

◆ AsmReadDr5()

UINTN EFIAPI AsmReadDr5 ( VOID )

Reads the current value of Debug Register 5 (DR5).

Reads and returns the current value of DR5. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 5 (DR5).

Definition at line 477 of file GccInlinePriv.c.

◆ AsmReadDr6()

UINTN EFIAPI AsmReadDr6 ( VOID )

Reads the current value of Debug Register 6 (DR6).

Reads and returns the current value of DR6. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 6 (DR6).

Definition at line 503 of file GccInlinePriv.c.

◆ AsmReadDr7()

UINTN EFIAPI AsmReadDr7 ( VOID )

Reads the current value of Debug Register 7 (DR7).

Reads and returns the current value of DR7. This function is only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on X64.

Returns: The value of Debug Register 7 (DR7).

Definition at line 529 of file GccInlinePriv.c.

◆ AsmReadDs()

UINT16 EFIAPI AsmReadDs ( VOID )

Reads the current value of Data Segment Register (DS).

Reads and returns the current value of DS. This function is only available on IA-32 and X64.

Returns: The current value of DS.

Definition at line 779 of file GccInlinePriv.c.

◆ AsmReadEs()

UINT16 EFIAPI AsmReadEs ( VOID )

Reads the current value of Extra Segment Register (ES).

Reads and returns the current value of ES. This function is only available on IA-32 and X64.

Returns: The current value of ES.

Definition at line 804 of file GccInlinePriv.c.

◆ AsmReadFs()

UINT16 EFIAPI AsmReadFs ( VOID )

Reads the current value of FS Data Segment Register (FS).

Reads and returns the current value of FS. This function is only available on IA-32 and X64.

Returns: The current value of FS.

Definition at line 829 of file GccInlinePriv.c.

◆ AsmReadGs()

UINT16 EFIAPI AsmReadGs ( VOID )

Reads the current value of GS Data Segment Register (GS).

Reads and returns the current value of GS. This function is only available on IA-32 and X64.

Returns: The current value of GS.

Definition at line 854 of file GccInlinePriv.c.

◆ AsmReadLdtr()

UINT16 EFIAPI AsmReadLdtr ( VOID )

Reads the current Local Descriptor Table Register(LDTR) selector.

Reads and returns the current 16-bit LDTR descriptor value. This function is only available on IA-32 and X64.

Returns: The current selector of LDT.

Definition at line 1015 of file GccInlinePriv.c.

◆ AsmReadMsr64()

UINT64 EFIAPI AsmReadMsr64 ( IN UINT32 Index )

Returns a 64-bit Machine Specific Register(MSR).

Reads and returns the 64-bit MSR specified by Index. No parameter checking is performed on Index, and some Index values may cause CPU exceptions. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available on IA-32 and X64.

Parameters

Index The 32-bit MSR index to read.

Returns: The value of the MSR identified by Index.

Definition at line 60 of file GccInlinePriv.c.

◆ AsmReadPmc()

UINT64 EFIAPI AsmReadPmc ( IN UINT32 Index )

Reads the current value of a Performance Counter (PMC).

Reads and returns the current value of performance counter specified by Index. This function is only available on IA-32 and X64.

Parameters

Index The 32-bit Performance Counter index to read.

Returns: The value of the PMC specified by Index.

Definition at line 1064 of file GccInlinePriv.c.

◆ AsmReadSs()

UINT16 EFIAPI AsmReadSs ( VOID )

Reads the current value of Stack Segment Register (SS).

Reads and returns the current value of SS. This function is only available on IA-32 and X64.

Returns: The current value of SS.

Definition at line 879 of file GccInlinePriv.c.

◆ AsmReadTr()

UINT16 EFIAPI AsmReadTr ( VOID )

Reads the current value of Task Register (TR).

Reads and returns the current value of TR. This function is only available on IA-32 and X64.

Returns: The current value of TR.

Definition at line 904 of file GccInlinePriv.c.

◆ AsmWbinvd()

VOID EFIAPI AsmWbinvd ( VOID )

Executes a WBINVD instruction.

Executes a WBINVD instruction. This function is only available on IA-32 and X64.

Definition at line 1156 of file GccInlinePriv.c.

◆ AsmWriteCr0()

UINTN EFIAPI AsmWriteCr0 ( UINTN Cr0 )

Writes a value to Control Register 0 (CR0).

Writes and returns a new value to CR0. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Cr0	The value to write to CR0.

Returns: The value written to CR0.

Definition at line 248 of file GccInlinePriv.c.

◆ AsmWriteCr2()

UINTN EFIAPI AsmWriteCr2 ( UINTN Cr2 )

Writes a value to Control Register 2 (CR2).

Writes and returns a new value to CR2. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Cr2	The value to write to CR2.

Returns: The value written to CR2.

Definition at line 273 of file GccInlinePriv.c.

◆ AsmWriteCr3()

UINTN EFIAPI AsmWriteCr3 ( UINTN Cr3 )

Writes a value to Control Register 3 (CR3).

Writes and returns a new value to CR3. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Cr3	The value to write to CR3.

Returns: The value written to CR3.

Definition at line 298 of file GccInlinePriv.c.

◆ AsmWriteCr4()

UINTN EFIAPI AsmWriteCr4 ( UINTN Cr4 )

Writes a value to Control Register 4 (CR4).

Writes and returns a new value to CR4. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Cr4	The value to write to CR4.

Returns: The value written to CR4.

Definition at line 323 of file GccInlinePriv.c.

◆ AsmWriteDr0()

UINTN EFIAPI AsmWriteDr0 ( UINTN Dr0 )

Writes a value to Debug Register 0 (DR0).

Writes and returns a new value to DR0. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr0	The value to write to Dr0.

Returns: The value written to Debug Register 0 (DR0).

Definition at line 556 of file GccInlinePriv.c.

◆ AsmWriteDr1()

UINTN EFIAPI AsmWriteDr1 ( UINTN Dr1 )

Writes a value to Debug Register 1 (DR1).

Writes and returns a new value to DR1. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr1	The value to write to Dr1.

Returns: The value written to Debug Register 1 (DR1).

Definition at line 581 of file GccInlinePriv.c.

◆ AsmWriteDr2()

UINTN EFIAPI AsmWriteDr2 ( UINTN Dr2 )

Writes a value to Debug Register 2 (DR2).

Writes and returns a new value to DR2. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr2	The value to write to Dr2.

Returns: The value written to Debug Register 2 (DR2).

Definition at line 606 of file GccInlinePriv.c.

◆ AsmWriteDr3()

UINTN EFIAPI AsmWriteDr3 ( UINTN Dr3 )

Writes a value to Debug Register 3 (DR3).

Writes and returns a new value to DR3. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr3	The value to write to Dr3.

Returns: The value written to Debug Register 3 (DR3).

Definition at line 631 of file GccInlinePriv.c.

◆ AsmWriteDr4()

UINTN EFIAPI AsmWriteDr4 ( UINTN Dr4 )

Writes a value to Debug Register 4 (DR4).

Writes and returns a new value to DR4. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr4	The value to write to Dr4.

Returns: The value written to Debug Register 4 (DR4).

Definition at line 656 of file GccInlinePriv.c.

◆ AsmWriteDr5()

UINTN EFIAPI AsmWriteDr5 ( UINTN Dr5 )

Writes a value to Debug Register 5 (DR5).

Writes and returns a new value to DR5. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr5	The value to write to Dr5.

Returns: The value written to Debug Register 5 (DR5).

Definition at line 681 of file GccInlinePriv.c.

◆ AsmWriteDr6()

UINTN EFIAPI AsmWriteDr6 ( UINTN Dr6 )

Writes a value to Debug Register 6 (DR6).

Writes and returns a new value to DR6. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr6	The value to write to Dr6.

Returns: The value written to Debug Register 6 (DR6).

Definition at line 706 of file GccInlinePriv.c.

◆ AsmWriteDr7()

UINTN EFIAPI AsmWriteDr7 ( UINTN Dr7 )

Writes a value to Debug Register 7 (DR7).

Writes and returns a new value to DR7. This function is only available on IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.

Parameters

Dr7	The value to write to Dr7.

Returns: The value written to Debug Register 7 (DR7).

Definition at line 731 of file GccInlinePriv.c.

◆ AsmWriteLdtr()

VOID EFIAPI AsmWriteLdtr ( IN UINT16 Ldtr )

Writes the current Local Descriptor Table Register (GDTR) selector.

Writes and the current LDTR descriptor specified by Ldtr. This function is only available on IA-32 and X64.

Parameters

Ldtr	16-bit LDTR selector value.

Definition at line 1040 of file GccInlinePriv.c.

◆ AsmWriteMsr64()

UINT64 EFIAPI AsmWriteMsr64	(	IN UINT32	Index,
		IN UINT64	Value
	)

Writes a 64-bit value to a Machine Specific Register(MSR), and returns the value.

Writes the 64-bit value specified by Value to the MSR specified by Index. The 64-bit value written to the MSR is returned. No parameter checking is performed on Index or Value, and some of these may cause CPU exceptions. The caller must either guarantee that Index and Value are valid, or the caller must establish proper exception handlers. This function is only available on IA-32 and X64.

Parameters

Index	The 32-bit MSR index to write.
Value	The 64-bit value to write to the MSR.

Returns: Value

Definition at line 104 of file GccInlinePriv.c.

◆ DisableInterrupts()

VOID EFIAPI DisableInterrupts ( VOID )

Disables CPU interrupts.

Definition at line 37 of file GccInlinePriv.c.

◆ EnableInterrupts()

VOID EFIAPI EnableInterrupts ( VOID )

Enables CPU interrupts.

Definition at line 22 of file GccInlinePriv.c.

◆ InternalX86ReadGdtr()

VOID EFIAPI InternalX86ReadGdtr ( OUT IA32_DESCRIPTOR * Gdtr )

Reads the current Global Descriptor Table Register(GDTR) descriptor.

Reads and returns the current GDTR descriptor and returns it in Gdtr. This function is only available on IA-32 and X64.

Parameters

Gdtr	The pointer to a GDTR descriptor.

Definition at line 929 of file GccInlinePriv.c.

◆ InternalX86ReadIdtr()

VOID EFIAPI InternalX86ReadIdtr ( OUT IA32_DESCRIPTOR * Idtr )

Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.

Reads and returns the current IDTR descriptor and returns it in Idtr. This function is only available on IA-32 and X64.

Parameters

Idtr	The pointer to a IDTR descriptor.

Definition at line 972 of file GccInlinePriv.c.

◆ InternalX86WriteGdtr()

VOID EFIAPI InternalX86WriteGdtr ( IN CONST IA32_DESCRIPTOR * Gdtr )

Writes the current Global Descriptor Table Register (GDTR) descriptor.

Writes and the current GDTR descriptor specified by Gdtr. This function is only available on IA-32 and X64.

Parameters

Gdtr	The pointer to a GDTR descriptor.

Definition at line 950 of file GccInlinePriv.c.

◆ InternalX86WriteIdtr()

VOID EFIAPI InternalX86WriteIdtr ( IN CONST IA32_DESCRIPTOR * Idtr )

Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.

Writes the current IDTR descriptor and returns it in Idtr. This function is only available on IA-32 and X64.

Parameters

Idtr	The pointer to a IDTR descriptor.

Definition at line 993 of file GccInlinePriv.c.

Functions

Detailed Description

Function Documentation

◆ AsmFlushCacheLine()

◆ AsmInvd()

◆ AsmMonitor()

◆ AsmMwait()

◆ AsmReadCr0()

◆ AsmReadCr2()

◆ AsmReadCr3()

◆ AsmReadCr4()

◆ AsmReadCs()

◆ AsmReadDr0()

◆ AsmReadDr1()

◆ AsmReadDr2()

◆ AsmReadDr3()

◆ AsmReadDr4()

◆ AsmReadDr5()

◆ AsmReadDr6()

◆ AsmReadDr7()

◆ AsmReadDs()

◆ AsmReadEs()

◆ AsmReadFs()

◆ AsmReadGs()

◆ AsmReadLdtr()

◆ AsmReadMsr64()

◆ AsmReadPmc()

◆ AsmReadSs()

◆ AsmReadTr()

◆ AsmWbinvd()

◆ AsmWriteCr0()

◆ AsmWriteCr2()

◆ AsmWriteCr3()

◆ AsmWriteCr4()

◆ AsmWriteDr0()

◆ AsmWriteDr1()

◆ AsmWriteDr2()

◆ AsmWriteDr3()

◆ AsmWriteDr4()

◆ AsmWriteDr5()

◆ AsmWriteDr6()

◆ AsmWriteDr7()

◆ AsmWriteLdtr()

◆ AsmWriteMsr64()

◆ DisableInterrupts()

◆ EnableInterrupts()

◆ InternalX86ReadGdtr()

◆ InternalX86ReadIdtr()

◆ InternalX86WriteGdtr()

◆ InternalX86WriteIdtr()