XeonDMsr.h

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#ifndef __XEON_D_MSR_H__
#define __XEON_D_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x4F || \
    DisplayModel == 0x56    \
    )                       \
   )
 
#define MSR_XEON_D_PPIN_CTL  0x0000004E
 
typedef union {
  struct {
    UINT32    LockOut     : 1;
    UINT32    Enable_PPIN : 1;
    UINT32    Reserved1   : 30;
    UINT32    Reserved2   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_PPIN_CTL_REGISTER;
 
#define MSR_XEON_D_PPIN  0x0000004F
 
#define MSR_XEON_D_PLATFORM_INFO  0x000000CE
 
typedef union {
  struct {
    UINT32    Reserved1              : 8;
    UINT32    MaximumNonTurboRatio   : 8;
    UINT32    Reserved2              : 7;
    UINT32    PPIN_CAP               : 1;
    UINT32    Reserved3              : 4;
    UINT32    RatioLimit             : 1;
    UINT32    TDPLimit               : 1;
    UINT32    TJOFFSET               : 1;
    UINT32    Reserved4              : 1;
    UINT32    Reserved5              : 8;
    UINT32    MaximumEfficiencyRatio : 8;
    UINT32    Reserved6              : 16;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_PLATFORM_INFO_REGISTER;
 
#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL  0x000000E2
 
typedef union {
  struct {
    UINT32    Limit            : 3;
    UINT32    Reserved1        : 7;
    UINT32    IO_MWAIT         : 1;
    UINT32    Reserved2        : 4;
    UINT32    CFGLock          : 1;
    UINT32    CStateConversion : 1;
    UINT32    Reserved3        : 8;
    UINT32    C3AutoDemotion   : 1;
    UINT32    C1AutoDemotion   : 1;
    UINT32    C3Undemotion     : 1;
    UINT32    C1Undemotion     : 1;
    UINT32    CStateDemotion   : 1;
    UINT32    CStateUndemotion : 1;
    UINT32    Reserved4        : 1;
    UINT32    Reserved5        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;
 
#define MSR_XEON_D_IA32_MCG_CAP  0x00000179
 
typedef union {
  struct {
    UINT32    Count       : 8;
    UINT32    MCG_CTL_P   : 1;
    UINT32    MCG_EXT_P   : 1;
    UINT32    MCP_CMCI_P  : 1;
    UINT32    MCG_TES_P   : 1;
    UINT32    Reserved1   : 4;
    UINT32    MCG_EXT_CNT : 8;
    UINT32    MCG_SER_P   : 1;
    UINT32    MCG_EM_P    : 1;
    UINT32    MCG_ELOG_P  : 1;
    UINT32    Reserved2   : 5;
    UINT32    Reserved3   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_IA32_MCG_CAP_REGISTER;
 
#define MSR_XEON_D_SMM_MCA_CAP  0x0000017D
 
typedef union {
  struct {
    UINT32    Reserved1            : 32;
    UINT32    Reserved2            : 26;
    UINT32    SMM_Code_Access_Chk  : 1;
    UINT32    Long_Flow_Indication : 1;
    UINT32    Reserved3            : 4;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_SMM_MCA_CAP_REGISTER;
 
#define MSR_XEON_D_TEMPERATURE_TARGET  0x000001A2
 
typedef union {
  struct {
    UINT32    Reserved1           : 16;
    UINT32    TemperatureTarget   : 8;
    UINT32    TCCActivationOffset : 4;
    UINT32    Reserved2           : 4;
    UINT32    Reserved3           : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;
 
#define MSR_XEON_D_TURBO_RATIO_LIMIT  0x000001AD
 
typedef union {
  struct {
    UINT32    Maximum1C : 8;
    UINT32    Maximum2C : 8;
    UINT32    Maximum3C : 8;
    UINT32    Maximum4C : 8;
    UINT32    Maximum5C : 8;
    UINT32    Maximum6C : 8;
    UINT32    Maximum7C : 8;
    UINT32    Maximum8C : 8;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;
 
#define MSR_XEON_D_TURBO_RATIO_LIMIT1  0x000001AE
 
typedef union {
  struct {
    UINT32    Maximum9C  : 8;
    UINT32    Maximum10C : 8;
    UINT32    Maximum11C : 8;
    UINT32    Maximum12C : 8;
    UINT32    Maximum13C : 8;
    UINT32    Maximum14C : 8;
    UINT32    Maximum15C : 8;
    UINT32    Maximum16C : 8;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;
 
#define MSR_XEON_D_RAPL_POWER_UNIT  0x00000606
 
typedef union {
  struct {
    UINT32    PowerUnits        : 4;
    UINT32    Reserved1         : 4;
    UINT32    EnergyStatusUnits : 5;
    UINT32    Reserved2         : 3;
    UINT32    TimeUnits         : 4;
    UINT32    Reserved3         : 12;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;
 
#define MSR_XEON_D_DRAM_POWER_LIMIT  0x00000618
 
#define MSR_XEON_D_DRAM_ENERGY_STATUS  0x00000619
 
typedef union {
  struct {
    UINT32    Energy   : 32;
    UINT32    Reserved : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;
 
#define MSR_XEON_D_DRAM_PERF_STATUS  0x0000061B
 
#define MSR_XEON_D_DRAM_POWER_INFO  0x0000061C
 
#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT  0x00000620
 
typedef union {
  struct {
    UINT32    MAX_RATIO : 7;
    UINT32    Reserved1 : 1;
    UINT32    MIN_RATIO : 7;
    UINT32    Reserved2 : 17;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;
 
#define MSR_XEON_D_PP0_ENERGY_STATUS  0x00000639
 
#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS  0x00000690
 
typedef union {
  struct {
    UINT32    PROCHOT_Status                                   : 1;
    UINT32    ThermalStatus                                    : 1;
    UINT32    PowerBudgetManagementStatus                      : 1;
    UINT32    PlatformConfigurationServicesStatus              : 1;
    UINT32    Reserved1                                        : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlStatus : 1;
    UINT32    VRThermAlertStatus                               : 1;
    UINT32    Reserved2                                        : 1;
    UINT32    ElectricalDesignPointStatus                      : 1;
    UINT32    Reserved3                                        : 1;
    UINT32    MultiCoreTurboStatus                             : 1;
    UINT32    Reserved4                                        : 2;
    UINT32    FrequencyP1Status                                : 1;
    UINT32    TurboFrequencyLimitingStatus                     : 1;
    UINT32    FrequencyLimitingStatus                          : 1;
    UINT32    PROCHOT_Log                                      : 1;
    UINT32    ThermalLog                                       : 1;
    UINT32    PowerBudgetManagementLog                         : 1;
    UINT32    PlatformConfigurationServicesLog                 : 1;
    UINT32    Reserved5                                        : 1;
    UINT32    AutonomousUtilizationBasedFrequencyControlLog    : 1;
    UINT32    VRThermAlertLog                                  : 1;
    UINT32    Reserved6                                        : 1;
    UINT32    ElectricalDesignPointLog                         : 1;
    UINT32    Reserved7                                        : 1;
    UINT32    MultiCoreTurboLog                                : 1;
    UINT32    Reserved8                                        : 2;
    UINT32    CoreFrequencyP1Log                               : 1;
    UINT32    TurboFrequencyLimitingLog                        : 1;
    UINT32    CoreFrequencyLimitingLog                         : 1;
    UINT32    Reserved9                                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;
 
#define MSR_XEON_D_IA32_QM_EVTSEL  0x00000C8D
 
typedef union {
  struct {
    UINT32    EventID   : 8;
    UINT32    Reserved1 : 24;
    UINT32    RMID      : 10;
    UINT32    Reserved2 : 22;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;
 
#define MSR_XEON_D_IA32_PQR_ASSOC  0x00000C8F
 
typedef union {
  struct {
    UINT32    RMID      : 10;
    UINT32    Reserved1 : 22;
    UINT32    COS       : 20;
    UINT32    Reserved2 : 12;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;
 
#define MSR_XEON_D_IA32_L3_QOS_MASK_0   0x00000C90
#define MSR_XEON_D_IA32_L3_QOS_MASK_1   0x00000C91
#define MSR_XEON_D_IA32_L3_QOS_MASK_2   0x00000C92
#define MSR_XEON_D_IA32_L3_QOS_MASK_3   0x00000C93
#define MSR_XEON_D_IA32_L3_QOS_MASK_4   0x00000C94
#define MSR_XEON_D_IA32_L3_QOS_MASK_5   0x00000C95
#define MSR_XEON_D_IA32_L3_QOS_MASK_6   0x00000C96
#define MSR_XEON_D_IA32_L3_QOS_MASK_7   0x00000C97
#define MSR_XEON_D_IA32_L3_QOS_MASK_8   0x00000C98
#define MSR_XEON_D_IA32_L3_QOS_MASK_9   0x00000C99
#define MSR_XEON_D_IA32_L3_QOS_MASK_10  0x00000C9A
#define MSR_XEON_D_IA32_L3_QOS_MASK_11  0x00000C9B
#define MSR_XEON_D_IA32_L3_QOS_MASK_12  0x00000C9C
#define MSR_XEON_D_IA32_L3_QOS_MASK_13  0x00000C9D
#define MSR_XEON_D_IA32_L3_QOS_MASK_14  0x00000C9E
#define MSR_XEON_D_IA32_L3_QOS_MASK_15  0x00000C9F
 
typedef union {
  struct {
    UINT32    CBM       : 20;
    UINT32    Reserved2 : 12;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;
 
#define MSR_XEON_D_TURBO_RATIO_LIMIT3  0x000001AC
 
typedef union {
  struct {
    UINT32    Reserved1                             : 32;
    UINT32    Reserved2                             : 31;
    UINT32    TurboRatioLimitConfigurationSemaphore : 1;
  } Bits;
  UINT64    Uint64;
} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;
 
#define MSR_XEON_D_IA32_L3_QOS_CFG  0x00000C81
 
typedef union {
  struct {
    UINT32    CAT       : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;
 
#endif