Data Structures
struct	HCSPARAMS1

union	XHC_HCSPARAMS1

struct	HCSPARAMS2

union	XHC_HCSPARAMS2

struct	HCCPARAMS

union	XHC_HCCPARAMS

struct	USB_CLASSC

struct	EFI_USB_HUB_DESCRIPTOR

struct	USB_PORT_STATE_MAP

struct	USB_CLEAR_PORT_MAP

Macros
#define	XHC_CAPLENGTH_OFFSET 0x00

#define	XHC_HCIVERSION_OFFSET 0x02

#define	XHC_HCSPARAMS1_OFFSET 0x04

#define	XHC_HCSPARAMS2_OFFSET 0x08

#define	XHC_HCSPARAMS3_OFFSET 0x0c

#define	XHC_HCCPARAMS_OFFSET 0x10

#define	XHC_DBOFF_OFFSET 0x14

#define	XHC_RTSOFF_OFFSET 0x18

#define	XHC_USBCMD_OFFSET 0x0000

#define	XHC_USBSTS_OFFSET 0x0004

#define	XHC_PAGESIZE_OFFSET 0x0008

#define	XHC_DNCTRL_OFFSET 0x0014

#define	XHC_CRCR_OFFSET 0x0018

#define	XHC_DCBAAP_OFFSET 0x0030

#define	XHC_CONFIG_OFFSET 0x0038

#define	XHC_PORTSC_OFFSET 0x0400

#define	XHC_MFINDEX_OFFSET 0x00

#define	XHC_IMAN_OFFSET 0x20

#define	XHC_IMOD_OFFSET 0x24

#define	XHC_ERSTSZ_OFFSET 0x28

#define	XHC_ERSTBA_OFFSET 0x30

#define	XHC_ERDP_OFFSET 0x38

#define	XHC_USBCMD_RUN BIT0

#define	XHC_USBCMD_RESET BIT1

#define	XHC_USBCMD_INTE BIT2

#define	XHC_USBCMD_HSEE BIT3

#define	XHC_USBSTS_HALT BIT0

#define	XHC_USBSTS_HSE BIT2

#define	XHC_USBSTS_EINT BIT3

#define	XHC_USBSTS_PCD BIT4

#define	XHC_USBSTS_SSS BIT8

#define	XHC_USBSTS_RSS BIT9

#define	XHC_USBSTS_SRE BIT10

#define	XHC_USBSTS_CNR BIT11

#define	XHC_USBSTS_HCE BIT12

#define	XHC_PAGESIZE_MASK 0xFFFF

#define	XHC_CRCR_RCS BIT0

#define	XHC_CRCR_CS BIT1

#define	XHC_CRCR_CA BIT2

#define	XHC_CRCR_CRR BIT3

#define	XHC_CONFIG_MASK 0xFF

#define	XHC_PORTSC_CCS BIT0

#define	XHC_PORTSC_PED BIT1

#define	XHC_PORTSC_OCA BIT3

#define	XHC_PORTSC_RESET BIT4

#define	XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8)

#define	XHC_PORTSC_PP BIT9

#define	XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13)

#define	XHC_PORTSC_LWS BIT16

#define	XHC_PORTSC_CSC BIT17

#define	XHC_PORTSC_PEC BIT18

#define	XHC_PORTSC_WRC BIT19

#define	XHC_PORTSC_OCC BIT20

#define	XHC_PORTSC_PRC BIT21

#define	XHC_PORTSC_PLC BIT22

#define	XHC_PORTSC_CEC BIT23

#define	XHC_PORTSC_CAS BIT24

#define	XHC_HUB_PORTSC_CCS BIT0

#define	XHC_HUB_PORTSC_PED BIT1

#define	XHC_HUB_PORTSC_OCA BIT3

#define	XHC_HUB_PORTSC_RESET BIT4

#define	XHC_HUB_PORTSC_PP BIT9

#define	XHC_HUB_PORTSC_CSC BIT16

#define	XHC_HUB_PORTSC_PEC BIT17

#define	XHC_HUB_PORTSC_OCC BIT19

#define	XHC_HUB_PORTSC_PRC BIT20

#define	XHC_HUB_PORTSC_BHRC BIT21

#define	XHC_IMAN_IP BIT0

#define	XHC_IMAN_IE BIT1

#define	XHC_IMODI_MASK 0x0000FFFF

#define	XHC_IMODC_MASK 0xFFFF0000

Enumerations
enum	XHC_PORT_FEATURE { Usb3PortBHPortReset = 28 , Usb3PortBHPortResetChange = 29 , Usb3PortBHPortReset = 28 , Usb3PortBHPortResetChange = 29 }

Functions
UINT32	XhcPeiReadOpReg (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset)

VOID	XhcPeiWriteOpReg (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Data)

VOID	XhcPeiSetOpRegBit (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Bit)

VOID	XhcPeiClearOpRegBit (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Bit)

EFI_STATUS	XhcPeiWaitOpRegBit (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Bit, IN BOOLEAN WaitToSet, IN UINT32 Timeout)

VOID	XhcPeiWriteDoorBellReg (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Data)

UINT32	XhcPeiReadRuntimeReg (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset)

VOID	XhcPeiWriteRuntimeReg (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Data)

VOID	XhcPeiSetRuntimeRegBit (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Bit)

VOID	XhcPeiClearRuntimeRegBit (IN PEI_XHC_DEV *Xhc, IN UINT32 Offset, IN UINT32 Bit)

BOOLEAN	XhcPeiIsHalt (IN PEI_XHC_DEV *Xhc)

BOOLEAN	XhcPeiIsSysError (IN PEI_XHC_DEV *Xhc)

EFI_STATUS	XhcPeiResetHC (IN PEI_XHC_DEV *Xhc, IN UINT32 Timeout)

EFI_STATUS	XhcPeiHaltHC (IN PEI_XHC_DEV *Xhc, IN UINT32 Timeout)

EFI_STATUS	XhcPeiRunHC (IN PEI_XHC_DEV *Xhc, IN UINT32 Timeout)

Detailed Description

Private Header file for Usb Host Controller PEIM

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file XhciReg.h.

Macro Definition Documentation

◆ XHC_CAPLENGTH_OFFSET

#define XHC_CAPLENGTH_OFFSET 0x00

Definition at line 16 of file XhciReg.h.

◆ XHC_CONFIG_MASK

#define XHC_CONFIG_MASK 0xFF

Definition at line 72 of file XhciReg.h.

◆ XHC_CONFIG_OFFSET

#define XHC_CONFIG_OFFSET 0x0038

Definition at line 34 of file XhciReg.h.

◆ XHC_CRCR_CA

#define XHC_CRCR_CA BIT2

Definition at line 69 of file XhciReg.h.

◆ XHC_CRCR_CRR

#define XHC_CRCR_CRR BIT3

Definition at line 70 of file XhciReg.h.

◆ XHC_CRCR_CS

#define XHC_CRCR_CS BIT1

Definition at line 68 of file XhciReg.h.

◆ XHC_CRCR_OFFSET

#define XHC_CRCR_OFFSET 0x0018

Definition at line 32 of file XhciReg.h.

◆ XHC_CRCR_RCS

#define XHC_CRCR_RCS BIT0

Definition at line 67 of file XhciReg.h.

◆ XHC_DBOFF_OFFSET

#define XHC_DBOFF_OFFSET 0x14

Definition at line 22 of file XhciReg.h.

◆ XHC_DCBAAP_OFFSET

#define XHC_DCBAAP_OFFSET 0x0030

Definition at line 33 of file XhciReg.h.

◆ XHC_DNCTRL_OFFSET

#define XHC_DNCTRL_OFFSET 0x0014

Definition at line 31 of file XhciReg.h.

◆ XHC_ERDP_OFFSET

#define XHC_ERDP_OFFSET 0x38

Definition at line 45 of file XhciReg.h.

◆ XHC_ERSTBA_OFFSET

#define XHC_ERSTBA_OFFSET 0x30

Definition at line 44 of file XhciReg.h.

◆ XHC_ERSTSZ_OFFSET

#define XHC_ERSTSZ_OFFSET 0x28

Definition at line 43 of file XhciReg.h.

◆ XHC_HCCPARAMS_OFFSET

#define XHC_HCCPARAMS_OFFSET 0x10

Definition at line 21 of file XhciReg.h.

◆ XHC_HCIVERSION_OFFSET

#define XHC_HCIVERSION_OFFSET 0x02

Definition at line 17 of file XhciReg.h.

◆ XHC_HCSPARAMS1_OFFSET

#define XHC_HCSPARAMS1_OFFSET 0x04

Definition at line 18 of file XhciReg.h.

◆ XHC_HCSPARAMS2_OFFSET

#define XHC_HCSPARAMS2_OFFSET 0x08

Definition at line 19 of file XhciReg.h.

◆ XHC_HCSPARAMS3_OFFSET

#define XHC_HCSPARAMS3_OFFSET 0x0c

Definition at line 20 of file XhciReg.h.

◆ XHC_HUB_PORTSC_BHRC

#define XHC_HUB_PORTSC_BHRC BIT21

Definition at line 100 of file XhciReg.h.

◆ XHC_HUB_PORTSC_CCS

#define XHC_HUB_PORTSC_CCS BIT0

Definition at line 91 of file XhciReg.h.

◆ XHC_HUB_PORTSC_CSC

#define XHC_HUB_PORTSC_CSC BIT16

Definition at line 96 of file XhciReg.h.

◆ XHC_HUB_PORTSC_OCA

#define XHC_HUB_PORTSC_OCA BIT3

Definition at line 93 of file XhciReg.h.

◆ XHC_HUB_PORTSC_OCC

#define XHC_HUB_PORTSC_OCC BIT19

Definition at line 98 of file XhciReg.h.

◆ XHC_HUB_PORTSC_PEC

#define XHC_HUB_PORTSC_PEC BIT17

Definition at line 97 of file XhciReg.h.

◆ XHC_HUB_PORTSC_PED

#define XHC_HUB_PORTSC_PED BIT1

Definition at line 92 of file XhciReg.h.

◆ XHC_HUB_PORTSC_PP

#define XHC_HUB_PORTSC_PP BIT9

Definition at line 95 of file XhciReg.h.

◆ XHC_HUB_PORTSC_PRC

#define XHC_HUB_PORTSC_PRC BIT20

Definition at line 99 of file XhciReg.h.

◆ XHC_HUB_PORTSC_RESET

#define XHC_HUB_PORTSC_RESET BIT4

Definition at line 94 of file XhciReg.h.

◆ XHC_IMAN_IE

#define XHC_IMAN_IE BIT1

Definition at line 103 of file XhciReg.h.

◆ XHC_IMAN_IP

#define XHC_IMAN_IP BIT0

Definition at line 102 of file XhciReg.h.

◆ XHC_IMAN_OFFSET

#define XHC_IMAN_OFFSET 0x20

Definition at line 41 of file XhciReg.h.

◆ XHC_IMOD_OFFSET

#define XHC_IMOD_OFFSET 0x24

Definition at line 42 of file XhciReg.h.

◆ XHC_IMODC_MASK

#define XHC_IMODC_MASK 0xFFFF0000

Definition at line 106 of file XhciReg.h.

◆ XHC_IMODI_MASK

#define XHC_IMODI_MASK 0x0000FFFF

Definition at line 105 of file XhciReg.h.

◆ XHC_MFINDEX_OFFSET

#define XHC_MFINDEX_OFFSET 0x00

Definition at line 40 of file XhciReg.h.

◆ XHC_PAGESIZE_MASK

#define XHC_PAGESIZE_MASK 0xFFFF

Definition at line 65 of file XhciReg.h.

◆ XHC_PAGESIZE_OFFSET

#define XHC_PAGESIZE_OFFSET 0x0008

Definition at line 30 of file XhciReg.h.

◆ XHC_PORTSC_CAS

#define XHC_PORTSC_CAS BIT24

Definition at line 89 of file XhciReg.h.

◆ XHC_PORTSC_CCS

#define XHC_PORTSC_CCS BIT0

Definition at line 74 of file XhciReg.h.

◆ XHC_PORTSC_CEC

#define XHC_PORTSC_CEC BIT23

Definition at line 88 of file XhciReg.h.

◆ XHC_PORTSC_CSC

#define XHC_PORTSC_CSC BIT17

Definition at line 82 of file XhciReg.h.

◆ XHC_PORTSC_LWS

#define XHC_PORTSC_LWS BIT16

Definition at line 81 of file XhciReg.h.

◆ XHC_PORTSC_OCA

#define XHC_PORTSC_OCA BIT3

Definition at line 76 of file XhciReg.h.

◆ XHC_PORTSC_OCC

#define XHC_PORTSC_OCC BIT20

Definition at line 85 of file XhciReg.h.

◆ XHC_PORTSC_OFFSET

#define XHC_PORTSC_OFFSET 0x0400

Definition at line 35 of file XhciReg.h.

◆ XHC_PORTSC_PEC

#define XHC_PORTSC_PEC BIT18

Definition at line 83 of file XhciReg.h.

◆ XHC_PORTSC_PED

#define XHC_PORTSC_PED BIT1

Definition at line 75 of file XhciReg.h.

◆ XHC_PORTSC_PLC

#define XHC_PORTSC_PLC BIT22

Definition at line 87 of file XhciReg.h.

◆ XHC_PORTSC_PLS

#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8)

Definition at line 78 of file XhciReg.h.

◆ XHC_PORTSC_PP

#define XHC_PORTSC_PP BIT9

Definition at line 79 of file XhciReg.h.

◆ XHC_PORTSC_PRC

#define XHC_PORTSC_PRC BIT21

Definition at line 86 of file XhciReg.h.

◆ XHC_PORTSC_PS

#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13)

Definition at line 80 of file XhciReg.h.

◆ XHC_PORTSC_RESET

#define XHC_PORTSC_RESET BIT4

Definition at line 77 of file XhciReg.h.

◆ XHC_PORTSC_WRC

#define XHC_PORTSC_WRC BIT19

Definition at line 84 of file XhciReg.h.

◆ XHC_RTSOFF_OFFSET

#define XHC_RTSOFF_OFFSET 0x18

Definition at line 23 of file XhciReg.h.

◆ XHC_USBCMD_HSEE

#define XHC_USBCMD_HSEE BIT3

Definition at line 53 of file XhciReg.h.

◆ XHC_USBCMD_INTE

#define XHC_USBCMD_INTE BIT2

Definition at line 52 of file XhciReg.h.

◆ XHC_USBCMD_OFFSET

#define XHC_USBCMD_OFFSET 0x0000

Definition at line 28 of file XhciReg.h.

◆ XHC_USBCMD_RESET

#define XHC_USBCMD_RESET BIT1

Definition at line 51 of file XhciReg.h.

◆ XHC_USBCMD_RUN

#define XHC_USBCMD_RUN BIT0

Definition at line 50 of file XhciReg.h.

◆ XHC_USBSTS_CNR

#define XHC_USBSTS_CNR BIT11

Definition at line 62 of file XhciReg.h.

◆ XHC_USBSTS_EINT

#define XHC_USBSTS_EINT BIT3

Definition at line 57 of file XhciReg.h.

◆ XHC_USBSTS_HALT

#define XHC_USBSTS_HALT BIT0

Definition at line 55 of file XhciReg.h.

◆ XHC_USBSTS_HCE

#define XHC_USBSTS_HCE BIT12

Definition at line 63 of file XhciReg.h.

◆ XHC_USBSTS_HSE

#define XHC_USBSTS_HSE BIT2

Definition at line 56 of file XhciReg.h.

◆ XHC_USBSTS_OFFSET

#define XHC_USBSTS_OFFSET 0x0004

Definition at line 29 of file XhciReg.h.

◆ XHC_USBSTS_PCD

#define XHC_USBSTS_PCD BIT4

Definition at line 58 of file XhciReg.h.

◆ XHC_USBSTS_RSS

#define XHC_USBSTS_RSS BIT9

Definition at line 60 of file XhciReg.h.

◆ XHC_USBSTS_SRE

#define XHC_USBSTS_SRE BIT10

Definition at line 61 of file XhciReg.h.

◆ XHC_USBSTS_SSS

#define XHC_USBSTS_SSS BIT8

Definition at line 59 of file XhciReg.h.

Enumeration Type Documentation

◆ XHC_PORT_FEATURE

enum XHC_PORT_FEATURE

Definition at line 192 of file XhciReg.h.

Function Documentation

◆ XhcPeiClearOpRegBit()

VOID XhcPeiClearOpRegBit	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Clear one bit of the operational register while keeping other bits.

Parameters

Xhc	The XHCI device.
Offset	The offset of the operational register.
Bit	The bit mask of the register to clear.

Definition at line 136 of file XhcPeim.c.

◆ XhcPeiClearRuntimeRegBit()

VOID XhcPeiClearRuntimeRegBit	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Clear one bit of the runtime register while keeping other bits.

Parameters

Xhc	The XHCI device.
Offset	The offset of the runtime register.
Bit	The bit mask of the register to set.

Definition at line 302 of file XhcPeim.c.

◆ XhcPeiHaltHC()

EFI_STATUS XhcPeiHaltHC	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Timeout
	)

Halt the host controller.

Parameters

Xhc	The XHCI device.
Timeout	Time to wait before abort.

Return values

EFI_TIMEOUT	Failed to halt the controller before Timeout.
EFI_SUCCESS	The XHCI is halt.

Definition at line 402 of file XhcPeim.c.

◆ XhcPeiIsHalt()

BOOLEAN XhcPeiIsHalt ( IN PEI_XHC_DEV * Xhc )

Check whether Xhc is halted.

Parameters

Xhc	The XHCI device.

Return values

TRUE	The controller is halted.
FALSE	The controller isn't halted.

Definition at line 325 of file XhcPeim.c.

◆ XhcPeiIsSysError()

BOOLEAN XhcPeiIsSysError ( IN PEI_XHC_DEV * Xhc )

Check whether system error occurred.

Parameters

Xhc	The XHCI device.

Return values

TRUE	System error happened.
FALSE	No system error.

Definition at line 342 of file XhcPeim.c.

◆ XhcPeiReadOpReg()

UINT32 XhcPeiReadOpReg	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset
	)

Read XHCI Operation register.

Parameters

Xhc	The XHCI device.
Offset	The operation register offset.

Return values

the	register content read.

Definition at line 72 of file XhcPeim.c.

◆ XhcPeiReadRuntimeReg()

UINT32 XhcPeiReadRuntimeReg	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset
	)

Read XHCI runtime register.

Parameters

Xhc	The XHCI device.
Offset	The offset of the runtime register.

Returns: The register content read

Definition at line 237 of file XhcPeim.c.

◆ XhcPeiResetHC()

EFI_STATUS XhcPeiResetHC	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Timeout
	)

Reset the host controller.

Parameters

Xhc	The XHCI device.
Timeout	Time to wait before abort (in millisecond, ms).

Return values

EFI_TIMEOUT	The transfer failed due to time out.
Others	Failed to reset the host.

Definition at line 360 of file XhcPeim.c.

◆ XhcPeiRunHC()

EFI_STATUS XhcPeiRunHC	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Timeout
	)

Set the XHCI to run.

Parameters

Xhc	The XHCI device.
Timeout	Time to wait before abort.

Return values

EFI_SUCCESS	The XHCI is running.
Others	Failed to set the XHCI to run.

Definition at line 426 of file XhcPeim.c.

◆ XhcPeiSetOpRegBit()

VOID XhcPeiSetOpRegBit	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Set one bit of the operational register while keeping other bits.

Parameters

Xhc	The XHCI device.
Offset	The offset of the operational register.
Bit	The bit mask of the register to set.

Definition at line 114 of file XhcPeim.c.

◆ XhcPeiSetRuntimeRegBit()

VOID XhcPeiSetRuntimeRegBit	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Bit
	)

Set one bit of the runtime register while keeping other bits.

Parameters

Xhc	The XHCI device.
Offset	The offset of the runtime register.
Bit	The bit mask of the register to set.

Definition at line 280 of file XhcPeim.c.

◆ XhcPeiWaitOpRegBit()

EFI_STATUS XhcPeiWaitOpRegBit	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Bit,
		IN BOOLEAN	WaitToSet,
		IN UINT32	Timeout
	)

Wait the operation register's bit as specified by Bit to be set (or clear).

Parameters

Xhc	The XHCI device.
Offset	The offset of the operational register.
Bit	The bit of the register to wait for.
WaitToSet	Wait the bit to set or clear.
Timeout	The time to wait before abort (in millisecond, ms).

Return values

EFI_SUCCESS	The bit successfully changed by host controller.
EFI_TIMEOUT	The time out occurred.

Wait the operation register's bit as specified by Bit to become set (or clear).

Parameters

Xhc	The XHCI device.
Offset	The offset of the operational register.
Bit	The bit mask of the register to wait for.
WaitToSet	Wait the bit to set or clear.
Timeout	The time to wait before abort (in millisecond, ms).

Return values

EFI_SUCCESS	The bit successfully changed by host controller.
EFI_TIMEOUT	The time out occurred.

Definition at line 164 of file XhcPeim.c.

◆ XhcPeiWriteDoorBellReg()

VOID XhcPeiWriteDoorBellReg	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Data
	)

Write the data to the XHCI door bell register.

Parameters

Xhc	The XHCI device.
Offset	The offset of the door bell register.
Data	The data to write.

Definition at line 216 of file XhcPeim.c.

◆ XhcPeiWriteOpReg()

VOID XhcPeiWriteOpReg	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Data
	)

Write the data to the XHCI operation register.

Parameters

Xhc	The XHCI device.
Offset	The operation register offset.
Data	The data to write.

Definition at line 94 of file XhcPeim.c.

◆ XhcPeiWriteRuntimeReg()

VOID XhcPeiWriteRuntimeReg	(	IN PEI_XHC_DEV *	Xhc,
		IN UINT32	Offset,
		IN UINT32	Data
	)

Write the data to the XHCI runtime register.

Parameters

Xhc	The XHCI device.
Offset	The offset of the runtime register.
Data	The data to write.

Definition at line 260 of file XhcPeim.c.

Data Structures

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ XHC_CAPLENGTH_OFFSET

◆ XHC_CONFIG_MASK

◆ XHC_CONFIG_OFFSET

◆ XHC_CRCR_CA

◆ XHC_CRCR_CRR

◆ XHC_CRCR_CS

◆ XHC_CRCR_OFFSET

◆ XHC_CRCR_RCS

◆ XHC_DBOFF_OFFSET

◆ XHC_DCBAAP_OFFSET

◆ XHC_DNCTRL_OFFSET

◆ XHC_ERDP_OFFSET

◆ XHC_ERSTBA_OFFSET

◆ XHC_ERSTSZ_OFFSET

◆ XHC_HCCPARAMS_OFFSET

◆ XHC_HCIVERSION_OFFSET

◆ XHC_HCSPARAMS1_OFFSET

◆ XHC_HCSPARAMS2_OFFSET

◆ XHC_HCSPARAMS3_OFFSET

◆ XHC_HUB_PORTSC_BHRC

◆ XHC_HUB_PORTSC_CCS

◆ XHC_HUB_PORTSC_CSC

◆ XHC_HUB_PORTSC_OCA

◆ XHC_HUB_PORTSC_OCC

◆ XHC_HUB_PORTSC_PEC

◆ XHC_HUB_PORTSC_PED

◆ XHC_HUB_PORTSC_PP

◆ XHC_HUB_PORTSC_PRC

◆ XHC_HUB_PORTSC_RESET

◆ XHC_IMAN_IE

◆ XHC_IMAN_IP

◆ XHC_IMAN_OFFSET

◆ XHC_IMOD_OFFSET

◆ XHC_IMODC_MASK

◆ XHC_IMODI_MASK

◆ XHC_MFINDEX_OFFSET

◆ XHC_PAGESIZE_MASK

◆ XHC_PAGESIZE_OFFSET

◆ XHC_PORTSC_CAS

◆ XHC_PORTSC_CCS

◆ XHC_PORTSC_CEC

◆ XHC_PORTSC_CSC

◆ XHC_PORTSC_LWS

◆ XHC_PORTSC_OCA

◆ XHC_PORTSC_OCC

◆ XHC_PORTSC_OFFSET

◆ XHC_PORTSC_PEC

◆ XHC_PORTSC_PED

◆ XHC_PORTSC_PLC

◆ XHC_PORTSC_PLS

◆ XHC_PORTSC_PP

◆ XHC_PORTSC_PRC

◆ XHC_PORTSC_PS

◆ XHC_PORTSC_RESET

◆ XHC_PORTSC_WRC

◆ XHC_RTSOFF_OFFSET

◆ XHC_USBCMD_HSEE

◆ XHC_USBCMD_INTE

◆ XHC_USBCMD_OFFSET

◆ XHC_USBCMD_RESET

◆ XHC_USBCMD_RUN

◆ XHC_USBSTS_CNR

◆ XHC_USBSTS_EINT

◆ XHC_USBSTS_HALT

◆ XHC_USBSTS_HCE

◆ XHC_USBSTS_HSE

◆ XHC_USBSTS_OFFSET

◆ XHC_USBSTS_PCD

◆ XHC_USBSTS_RSS

◆ XHC_USBSTS_SRE

◆ XHC_USBSTS_SSS

Enumeration Type Documentation

◆ XHC_PORT_FEATURE

Function Documentation