ArmLib.h File Reference

#include <Uefi/UefiBaseType.h>

Go to the source code of this file.

Data Structures
struct	ARM_MEMORY_REGION_DESCRIPTOR

Macros
#define	EFI_MEMORY_CACHETYPE_MASK
#define	ARM_CPU_IMPLEMENTER_MASK   (0xFFU << 24)
#define	ARM_CPU_IMPLEMENTER_ARMLTD   (0x41U << 24)
#define	ARM_CPU_IMPLEMENTER_DEC   (0x44U << 24)
#define	ARM_CPU_IMPLEMENTER_MOT   (0x4DU << 24)
#define	ARM_CPU_IMPLEMENTER_QUALCOMM   (0x51U << 24)
#define	ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)
#define	ARM_CPU_PRIMARY_PART_MASK   (0xFFF << 4)
#define	ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)
#define	ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)
#define	ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)
#define	ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)
#define	ARM_CPU_PRIMARY_PART_CORTEXA15   (0xC0F << 4)
#define	ARM_CORE_AFF0   0xFF
#define	ARM_CORE_AFF1   (0xFF << 8)
#define	ARM_CORE_AFF2   (0xFF << 16)
#define	ARM_CORE_AFF3   (0xFFULL << 32)
#define	ARM_CORE_MASK   ARM_CORE_AFF0
#define	ARM_CLUSTER_MASK   ARM_CORE_AFF1
#define	GET_CORE_ID(MpId)   ((MpId) & ARM_CORE_MASK)
#define	GET_CLUSTER_ID(MpId)   (((MpId) & ARM_CLUSTER_MASK) >> 8)
#define	GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
#define	GET_MPIDR_AFF0(MpId)   ((MpId) & ARM_CORE_AFF0)
#define	GET_MPIDR_AFF1(MpId)   (((MpId) & ARM_CORE_AFF1) >> 8)
#define	GET_MPIDR_AFF2(MpId)   (((MpId) & ARM_CORE_AFF2) >> 16)
#define	GET_MPIDR_AFF3(MpId)   (((MpId) & ARM_CORE_AFF3) >> 32)
#define	GET_MPIDR_AFFINITY_BITS(MpId)   ((MpId) & 0xFF00FFFFFF)
#define	PRIMARY_CORE_ID   (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
#define	MPIDR_MT_BIT   BIT24
#define	ARM_ARCH_TIMER_ENABLE   (1 << 0)
#define	ARM_ARCH_TIMER_IMASK   (1 << 1)
#define	ARM_ARCH_TIMER_ISTATUS   (1 << 2)

Typedefs
typedef VOID(*	CACHE_OPERATION) (VOID)
typedef VOID(*	LINE_OPERATION) (UINTN)

Enumerations
enum	ARM_MEMORY_REGION_ATTRIBUTES {   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0 , ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK , ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE , ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO ,   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP , ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH , ARM_MEMORY_REGION_ATTRIBUTE_DEVICE }
enum	ARM_PROCESSOR_MODE {   ARM_PROCESSOR_MODE_USER = 0x10 , ARM_PROCESSOR_MODE_FIQ = 0x11 , ARM_PROCESSOR_MODE_IRQ = 0x12 , ARM_PROCESSOR_MODE_SUPERVISOR = 0x13 ,   ARM_PROCESSOR_MODE_ABORT = 0x17 , ARM_PROCESSOR_MODE_HYP = 0x1A , ARM_PROCESSOR_MODE_UNDEFINED = 0x1B , ARM_PROCESSOR_MODE_SYSTEM = 0x1F ,   ARM_PROCESSOR_MODE_MASK = 0x1F }

Functions
UINTN	ReadCCSIDR (IN UINT32 CSSELR)
UINT32	ReadCCSIDR2 (IN UINT32 CSSELR)
UINT32	ReadCLIDR (VOID)
UINTN EFIAPI	ArmDataCacheLineLength (VOID)
UINTN EFIAPI	ArmInstructionCacheLineLength (VOID)
UINTN EFIAPI	ArmCacheWritebackGranule (VOID)
UINTN EFIAPI	ArmIsArchTimerImplemented (VOID)
UINTN EFIAPI	ArmCacheInfo (VOID)
BOOLEAN EFIAPI	ArmIsMpCore (VOID)
VOID EFIAPI	ArmInvalidateInstructionCache (VOID)
VOID EFIAPI	ArmInvalidateDataCacheEntryByMVA (IN UINTN Address)
VOID EFIAPI	ArmCleanDataCacheEntryToPoUByMVA (IN UINTN Address)
VOID EFIAPI	ArmInvalidateInstructionCacheEntryToPoUByMVA (IN UINTN Address)
VOID EFIAPI	ArmCleanDataCacheEntryByMVA (IN UINTN Address)
VOID EFIAPI	ArmCleanInvalidateDataCacheEntryByMVA (IN UINTN Address)
VOID EFIAPI	ArmEnableDataCache (VOID)
VOID EFIAPI	ArmDisableDataCache (VOID)
VOID EFIAPI	ArmEnableInstructionCache (VOID)
VOID EFIAPI	ArmDisableInstructionCache (VOID)
VOID EFIAPI	ArmEnableMmu (VOID)
VOID EFIAPI	ArmDisableMmu (VOID)
VOID EFIAPI	ArmEnableCachesAndMmu (VOID)
VOID EFIAPI	ArmDisableCachesAndMmu (VOID)
VOID EFIAPI	ArmEnableInterrupts (VOID)
UINTN EFIAPI	ArmDisableInterrupts (VOID)
BOOLEAN EFIAPI	ArmGetInterruptState (VOID)
VOID EFIAPI	ArmEnableAsynchronousAbort (VOID)
UINTN EFIAPI	ArmDisableAsynchronousAbort (VOID)
VOID EFIAPI	ArmEnableIrq (VOID)
UINTN EFIAPI	ArmDisableIrq (VOID)
VOID EFIAPI	ArmEnableFiq (VOID)
UINTN EFIAPI	ArmDisableFiq (VOID)
BOOLEAN EFIAPI	ArmGetFiqState (VOID)
VOID EFIAPI	ArmInvalidateTlb (VOID)
VOID EFIAPI	ArmUpdateTranslationTableEntry (IN VOID *TranslationTableEntry, IN VOID *Mva)
VOID EFIAPI	ArmSetDomainAccessControl (IN UINT32 Domain)
VOID EFIAPI	ArmSetTTBR0 (IN VOID *TranslationTableBase)
VOID EFIAPI	ArmSetTTBCR (IN UINT32 Bits)
VOID *EFIAPI	ArmGetTTBR0BaseAddress (VOID)
BOOLEAN EFIAPI	ArmMmuEnabled (VOID)
VOID EFIAPI	ArmEnableBranchPrediction (VOID)
VOID EFIAPI	ArmDisableBranchPrediction (VOID)
VOID EFIAPI	ArmSetLowVectors (VOID)
VOID EFIAPI	ArmSetHighVectors (VOID)
VOID EFIAPI	ArmDataMemoryBarrier (VOID)
VOID EFIAPI	ArmDataSynchronizationBarrier (VOID)
VOID EFIAPI	ArmInstructionSynchronizationBarrier (VOID)
VOID EFIAPI	ArmWriteVBar (IN UINTN VectorBase)
UINTN EFIAPI	ArmReadVBar (VOID)
VOID EFIAPI	ArmWriteAuxCr (IN UINT32 Bit)
UINT32 EFIAPI	ArmReadAuxCr (VOID)
VOID EFIAPI	ArmSetAuxCrBit (IN UINT32 Bits)
VOID EFIAPI	ArmUnsetAuxCrBit (IN UINT32 Bits)
VOID EFIAPI	ArmCallSEV (VOID)
VOID EFIAPI	ArmCallWFE (VOID)
VOID EFIAPI	ArmCallWFI (VOID)
UINTN EFIAPI	ArmReadMpidr (VOID)
UINTN EFIAPI	ArmReadMidr (VOID)
UINT32 EFIAPI	ArmReadCpacr (VOID)
VOID EFIAPI	ArmWriteCpacr (IN UINT32 Access)
VOID EFIAPI	ArmEnableVFP (VOID)
UINT32 EFIAPI	ArmReadSctlr (VOID)
VOID EFIAPI	ArmWriteSctlr (IN UINT32 Value)
UINTN EFIAPI	ArmReadHVBar (VOID)
VOID EFIAPI	ArmWriteHVBar (IN UINTN HypModeVectorBase)
UINTN EFIAPI	ArmReadCpuActlr (VOID)
VOID EFIAPI	ArmWriteCpuActlr (IN UINTN Val)
VOID EFIAPI	ArmSetCpuActlrBit (IN UINTN Bits)
VOID EFIAPI	ArmUnsetCpuActlrBit (IN UINTN Bits)
UINTN EFIAPI	ArmReadCntFrq (VOID)
VOID EFIAPI	ArmWriteCntFrq (UINTN FreqInHz)
UINT64 EFIAPI	ArmReadCntPct (VOID)
UINTN EFIAPI	ArmReadCntkCtl (VOID)
VOID EFIAPI	ArmWriteCntkCtl (UINTN Val)
UINTN EFIAPI	ArmReadCntpTval (VOID)
VOID EFIAPI	ArmWriteCntpTval (UINTN Val)
UINTN EFIAPI	ArmReadCntpCtl (VOID)
VOID EFIAPI	ArmWriteCntpCtl (UINTN Val)
UINTN EFIAPI	ArmReadCntvTval (VOID)
VOID EFIAPI	ArmWriteCntvTval (UINTN Val)
UINTN EFIAPI	ArmReadCntvCtl (VOID)
VOID EFIAPI	ArmWriteCntvCtl (UINTN Val)
UINT64 EFIAPI	ArmReadCntvCt (VOID)
UINT64 EFIAPI	ArmReadCntpCval (VOID)
VOID EFIAPI	ArmWriteCntpCval (UINT64 Val)
UINT64 EFIAPI	ArmReadCntvCval (VOID)
VOID EFIAPI	ArmWriteCntvCval (UINT64 Val)
UINT64 EFIAPI	ArmReadCntvOff (VOID)
VOID EFIAPI	ArmWriteCntvOff (UINT64 Val)
UINTN EFIAPI	ArmGetPhysicalAddressBits (VOID)
BOOLEAN EFIAPI	ArmHasGicSystemRegisters (VOID)
BOOLEAN EFIAPI	ArmHasCcidx (VOID)

Detailed Description

Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file ArmLib.h.

Macro Definition Documentation

ARM_ARCH_TIMER_ENABLE

#define ARM_ARCH_TIMER_ENABLE   (1 << 0)

Definition at line 556 of file ArmLib.h.

ARM_ARCH_TIMER_IMASK

#define ARM_ARCH_TIMER_IMASK   (1 << 1)

Definition at line 557 of file ArmLib.h.

ARM_ARCH_TIMER_ISTATUS

#define ARM_ARCH_TIMER_ISTATUS   (1 << 2)

Definition at line 558 of file ArmLib.h.

ARM_CLUSTER_MASK

#define ARM_CLUSTER_MASK   ARM_CORE_AFF1

Definition at line 103 of file ArmLib.h.

ARM_CORE_AFF0

#define ARM_CORE_AFF0   0xFF

Definition at line 97 of file ArmLib.h.

ARM_CORE_AFF1

#define ARM_CORE_AFF1   (0xFF << 8)

Definition at line 98 of file ArmLib.h.

ARM_CORE_AFF2

#define ARM_CORE_AFF2   (0xFF << 16)

Definition at line 99 of file ArmLib.h.

ARM_CORE_AFF3

#define ARM_CORE_AFF3   (0xFFULL << 32)

Definition at line 100 of file ArmLib.h.

ARM_CORE_MASK

#define ARM_CORE_MASK   ARM_CORE_AFF0

Definition at line 102 of file ArmLib.h.

ARM_CPU_IMPLEMENTER_ARMLTD

#define ARM_CPU_IMPLEMENTER_ARMLTD   (0x41U << 24)

Definition at line 81 of file ArmLib.h.

ARM_CPU_IMPLEMENTER_DEC

#define ARM_CPU_IMPLEMENTER_DEC   (0x44U << 24)

Definition at line 82 of file ArmLib.h.

ARM_CPU_IMPLEMENTER_MARVELL

#define ARM_CPU_IMPLEMENTER_MARVELL   (0x56U << 24)

Definition at line 85 of file ArmLib.h.

ARM_CPU_IMPLEMENTER_MASK

#define ARM_CPU_IMPLEMENTER_MASK   (0xFFU << 24)

Definition at line 80 of file ArmLib.h.

ARM_CPU_IMPLEMENTER_MOT

#define ARM_CPU_IMPLEMENTER_MOT   (0x4DU << 24)

Definition at line 83 of file ArmLib.h.

ARM_CPU_IMPLEMENTER_QUALCOMM

#define ARM_CPU_IMPLEMENTER_QUALCOMM   (0x51U << 24)

Definition at line 84 of file ArmLib.h.

ARM_CPU_PRIMARY_PART_CORTEXA15

#define ARM_CPU_PRIMARY_PART_CORTEXA15   (0xC0F << 4)

Definition at line 92 of file ArmLib.h.

ARM_CPU_PRIMARY_PART_CORTEXA5

#define ARM_CPU_PRIMARY_PART_CORTEXA5   (0xC05 << 4)

Definition at line 88 of file ArmLib.h.

ARM_CPU_PRIMARY_PART_CORTEXA7

#define ARM_CPU_PRIMARY_PART_CORTEXA7   (0xC07 << 4)

Definition at line 89 of file ArmLib.h.

ARM_CPU_PRIMARY_PART_CORTEXA8

#define ARM_CPU_PRIMARY_PART_CORTEXA8   (0xC08 << 4)

Definition at line 90 of file ArmLib.h.

ARM_CPU_PRIMARY_PART_CORTEXA9

#define ARM_CPU_PRIMARY_PART_CORTEXA9   (0xC09 << 4)

Definition at line 91 of file ArmLib.h.

ARM_CPU_PRIMARY_PART_MASK

#define ARM_CPU_PRIMARY_PART_MASK   (0xFFF << 4)

Definition at line 87 of file ArmLib.h.

EFI_MEMORY_CACHETYPE_MASK

#define EFI_MEMORY_CACHETYPE_MASK

Value:

                                     (EFI_MEMORY_UC | EFI_MEMORY_WC |  \
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \
                                     EFI_MEMORY_UCE)

Definition at line 24 of file ArmLib.h.

GET_CLUSTER_ID

#define GET_CLUSTER_ID

(

MpId

)

(((MpId) & ARM_CLUSTER_MASK) >> 8)

Definition at line 105 of file ArmLib.h.

GET_CORE_ID

#define GET_CORE_ID

(

MpId

)

((MpId) & ARM_CORE_MASK)

Definition at line 104 of file ArmLib.h.

GET_MPID

#define GET_MPID	(		ClusterId,
			CoreId
	)		(((ClusterId) << 8) | (CoreId))

Definition at line 106 of file ArmLib.h.

GET_MPIDR_AFF0

#define GET_MPIDR_AFF0

(

MpId

)

((MpId) & ARM_CORE_AFF0)

Definition at line 107 of file ArmLib.h.

GET_MPIDR_AFF1

#define GET_MPIDR_AFF1

(

MpId

)

(((MpId) & ARM_CORE_AFF1) >> 8)

Definition at line 108 of file ArmLib.h.

GET_MPIDR_AFF2

#define GET_MPIDR_AFF2

(

MpId

)

(((MpId) & ARM_CORE_AFF2) >> 16)

Definition at line 109 of file ArmLib.h.

GET_MPIDR_AFF3

#define GET_MPIDR_AFF3

(

MpId

)

(((MpId) & ARM_CORE_AFF3) >> 32)

Definition at line 110 of file ArmLib.h.

GET_MPIDR_AFFINITY_BITS

#define GET_MPIDR_AFFINITY_BITS

(

MpId

)

((MpId) & 0xFF00FFFFFF)

Definition at line 111 of file ArmLib.h.

MPIDR_MT_BIT

#define MPIDR_MT_BIT   BIT24

Definition at line 113 of file ArmLib.h.

PRIMARY_CORE_ID

#define PRIMARY_CORE_ID   (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)

Definition at line 112 of file ArmLib.h.

Typedef Documentation

CACHE_OPERATION

typedef VOID(* CACHE_OPERATION) (VOID)

Definition at line 55 of file ArmLib.h.

LINE_OPERATION

typedef VOID(* LINE_OPERATION) (UINTN)

Definition at line 58 of file ArmLib.h.

Enumeration Type Documentation

ARM_MEMORY_REGION_ATTRIBUTES

enum ARM_MEMORY_REGION_ATTRIBUTES

Definition at line 28 of file ArmLib.h.

ARM_PROCESSOR_MODE

enum ARM_PROCESSOR_MODE

Definition at line 65 of file ArmLib.h.

Function Documentation

ArmCacheWritebackGranule()

UINTN EFIAPI ArmCacheWritebackGranule

(

VOID

)

Definition at line 76 of file ArmLib.c.

ArmDataCacheLineLength()

UINTN EFIAPI ArmDataCacheLineLength

(

VOID

)

Definition at line 58 of file ArmLib.c.

ArmHasCcidx()

BOOLEAN EFIAPI ArmHasCcidx

(

VOID

)

Checks if CCIDX is implemented.

Return values

TRUE	CCIDX is implemented.
FALSE	CCIDX is not implemented.

Definition at line 43 of file AArch64Lib.c.

ArmHasGicSystemRegisters()

BOOLEAN EFIAPI ArmHasGicSystemRegisters

(

VOID

)

ID Register Helper functions Check whether the CPU supports the GIC system register interface (any version)

Returns

Whether GIC System Register Interface is supported

Check whether the CPU supports the GIC system register interface (any version)

Returns

Whether GIC System Register Interface is supported

Definition at line 29 of file AArch64Lib.c.

ArmInstructionCacheLineLength()

UINTN EFIAPI ArmInstructionCacheLineLength

(

VOID

)

Definition at line 67 of file ArmLib.c.

ArmInvalidateTlb()

VOID EFIAPI ArmInvalidateTlb

(

VOID

)

Invalidate Data and Instruction TLBs

ArmSetAuxCrBit()

VOID EFIAPI ArmSetAuxCrBit

(

IN UINT32

Bits

)

Definition at line 18 of file ArmLib.c.

ArmSetCpuActlrBit()

VOID EFIAPI ArmSetCpuActlrBit

(

IN UINTN

Bits

)

Definition at line 40 of file ArmLib.c.

ArmUnsetAuxCrBit()

VOID EFIAPI ArmUnsetAuxCrBit

(

IN UINT32

Bits

)

Definition at line 27 of file ArmLib.c.

ArmUnsetCpuActlrBit()

VOID EFIAPI ArmUnsetCpuActlrBit

(

IN UINTN

Bits

)

Definition at line 49 of file ArmLib.c.

ReadCCSIDR()

UINTN ReadCCSIDR

(

IN UINT32

CSSELR

)

Reads the CCSIDR register for the specified cache.

Parameters

CSSELR

The CSSELR cache selection register value.

Returns

The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode. Returns the contents of the CCSIDR register in AARCH32 mode.

ReadCCSIDR2()

UINT32 ReadCCSIDR2

(

IN UINT32

CSSELR

)

Reads the CCSIDR2 for the specified cache.

Parameters

CSSELR

The CSSELR cache selection register value

Returns

The contents of the CCSIDR2 register for the specified cache.

ReadCLIDR()

UINT32 ReadCLIDR

(

VOID

)

Reads the Cache Level ID (CLIDR) register.

Returns

The contents of the CLIDR_EL1 register.