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ArmLib.h
Go to the documentation of this file.
1
11#ifndef ARM_LIB_H_
12#define ARM_LIB_H_
13
14#include <Uefi/UefiBaseType.h>
15
16#ifdef MDE_CPU_ARM
17 #include <Arm/AArch32.h>
18#elif defined (MDE_CPU_AARCH64)
19 #include <AArch64/AArch64.h>
20#else
21 #error "Unknown chipset."
22#endif
23
24#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
25 EFI_MEMORY_WT | EFI_MEMORY_WB | \
26 EFI_MEMORY_UCE)
27
28typedef enum {
29 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
30 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
31
32 // On some platforms, memory mapped flash region is designed as not supporting
33 // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
34 // need.
35 // Do NOT use below two attributes if you are not sure.
36 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,
37
38 // Special region types for memory that must be mapped with read-only or
39 // non-execute permissions from the very start, e.g., to support the use
40 // of the WXN virtual memory control.
41 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_RO,
42 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP,
43
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
45 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
46} ARM_MEMORY_REGION_ATTRIBUTES;
47
48typedef struct {
49 EFI_PHYSICAL_ADDRESS PhysicalBase;
50 EFI_VIRTUAL_ADDRESS VirtualBase;
51 UINT64 Length;
52 ARM_MEMORY_REGION_ATTRIBUTES Attributes;
54
55typedef VOID (*CACHE_OPERATION)(
56 VOID
57 );
58typedef VOID (*LINE_OPERATION)(
59 UINTN
60 );
61
62//
63// ARM Processor Mode
64//
65typedef enum {
66 ARM_PROCESSOR_MODE_USER = 0x10,
67 ARM_PROCESSOR_MODE_FIQ = 0x11,
68 ARM_PROCESSOR_MODE_IRQ = 0x12,
69 ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
70 ARM_PROCESSOR_MODE_ABORT = 0x17,
71 ARM_PROCESSOR_MODE_HYP = 0x1A,
72 ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
73 ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
74 ARM_PROCESSOR_MODE_MASK = 0x1F
75} ARM_PROCESSOR_MODE;
76
77//
78// ARM Cpu IDs
79//
80#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
81#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
82#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
83#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
84#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
85#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
86
87#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
88#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
89#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
90#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
91#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
92#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
93
94//
95// ARM MP Core IDs
96//
97#define ARM_CORE_AFF0 0xFF
98#define ARM_CORE_AFF1 (0xFF << 8)
99#define ARM_CORE_AFF2 (0xFF << 16)
100#define ARM_CORE_AFF3 (0xFFULL << 32)
101
102#define ARM_CORE_MASK ARM_CORE_AFF0
103#define ARM_CLUSTER_MASK ARM_CORE_AFF1
104#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
105#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
106#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
107#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
108#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
109#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
110#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
111#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)
112#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
113#define MPIDR_MT_BIT BIT24
114
122UINTN
124 IN UINT32 CSSELR
125 );
126
133UINT32
135 IN UINT32 CSSELR
136 );
137
142UINT32
144 VOID
145 );
146
147UINTN
148EFIAPI
149ArmDataCacheLineLength (
150 VOID
151 );
152
153UINTN
154EFIAPI
155ArmInstructionCacheLineLength (
156 VOID
157 );
158
159UINTN
160EFIAPI
161ArmCacheWritebackGranule (
162 VOID
163 );
164
165UINTN
166EFIAPI
167ArmIsArchTimerImplemented (
168 VOID
169 );
170
171UINTN
172EFIAPI
173ArmCacheInfo (
174 VOID
175 );
176
177BOOLEAN
178EFIAPI
179ArmIsMpCore (
180 VOID
181 );
182
183VOID
184EFIAPI
185ArmInvalidateInstructionCache (
186 VOID
187 );
188
189VOID
190EFIAPI
191ArmInvalidateDataCacheEntryByMVA (
192 IN UINTN Address
193 );
194
195VOID
196EFIAPI
197ArmCleanDataCacheEntryToPoUByMVA (
198 IN UINTN Address
199 );
200
201VOID
202EFIAPI
203ArmInvalidateInstructionCacheEntryToPoUByMVA (
204 IN UINTN Address
205 );
206
207VOID
208EFIAPI
209ArmCleanDataCacheEntryByMVA (
210 IN UINTN Address
211 );
212
213VOID
214EFIAPI
215ArmCleanInvalidateDataCacheEntryByMVA (
216 IN UINTN Address
217 );
218
219VOID
220EFIAPI
221ArmEnableDataCache (
222 VOID
223 );
224
225VOID
226EFIAPI
227ArmDisableDataCache (
228 VOID
229 );
230
231VOID
232EFIAPI
233ArmEnableInstructionCache (
234 VOID
235 );
236
237VOID
238EFIAPI
239ArmDisableInstructionCache (
240 VOID
241 );
242
243VOID
244EFIAPI
245ArmEnableMmu (
246 VOID
247 );
248
249VOID
250EFIAPI
251ArmDisableMmu (
252 VOID
253 );
254
255VOID
256EFIAPI
257ArmEnableCachesAndMmu (
258 VOID
259 );
260
261VOID
262EFIAPI
263ArmDisableCachesAndMmu (
264 VOID
265 );
266
267VOID
268EFIAPI
269ArmEnableInterrupts (
270 VOID
271 );
272
273UINTN
274EFIAPI
275ArmDisableInterrupts (
276 VOID
277 );
278
279BOOLEAN
280EFIAPI
281ArmGetInterruptState (
282 VOID
283 );
284
285VOID
286EFIAPI
287ArmEnableAsynchronousAbort (
288 VOID
289 );
290
291UINTN
292EFIAPI
293ArmDisableAsynchronousAbort (
294 VOID
295 );
296
297VOID
298EFIAPI
299ArmEnableIrq (
300 VOID
301 );
302
303UINTN
304EFIAPI
305ArmDisableIrq (
306 VOID
307 );
308
309VOID
310EFIAPI
311ArmEnableFiq (
312 VOID
313 );
314
315UINTN
316EFIAPI
317ArmDisableFiq (
318 VOID
319 );
320
321BOOLEAN
322EFIAPI
323ArmGetFiqState (
324 VOID
325 );
326
330VOID
331EFIAPI
333 VOID
334 );
335
336VOID
337EFIAPI
338ArmUpdateTranslationTableEntry (
339 IN VOID *TranslationTableEntry,
340 IN VOID *Mva
341 );
342
343VOID
344EFIAPI
345ArmSetDomainAccessControl (
346 IN UINT32 Domain
347 );
348
349VOID
350EFIAPI
351ArmSetTTBR0 (
352 IN VOID *TranslationTableBase
353 );
354
355VOID
356EFIAPI
357ArmSetTTBCR (
358 IN UINT32 Bits
359 );
360
361VOID *
362EFIAPI
363ArmGetTTBR0BaseAddress (
364 VOID
365 );
366
367BOOLEAN
368EFIAPI
369ArmMmuEnabled (
370 VOID
371 );
372
373VOID
374EFIAPI
375ArmEnableBranchPrediction (
376 VOID
377 );
378
379VOID
380EFIAPI
381ArmDisableBranchPrediction (
382 VOID
383 );
384
385VOID
386EFIAPI
387ArmSetLowVectors (
388 VOID
389 );
390
391VOID
392EFIAPI
393ArmSetHighVectors (
394 VOID
395 );
396
397VOID
398EFIAPI
399ArmDataMemoryBarrier (
400 VOID
401 );
402
403VOID
404EFIAPI
405ArmDataSynchronizationBarrier (
406 VOID
407 );
408
409VOID
410EFIAPI
411ArmInstructionSynchronizationBarrier (
412 VOID
413 );
414
415VOID
416EFIAPI
417ArmWriteVBar (
418 IN UINTN VectorBase
419 );
420
421UINTN
422EFIAPI
423ArmReadVBar (
424 VOID
425 );
426
427VOID
428EFIAPI
429ArmWriteAuxCr (
430 IN UINT32 Bit
431 );
432
433UINT32
434EFIAPI
435ArmReadAuxCr (
436 VOID
437 );
438
439VOID
440EFIAPI
441ArmSetAuxCrBit (
442 IN UINT32 Bits
443 );
444
445VOID
446EFIAPI
447ArmUnsetAuxCrBit (
448 IN UINT32 Bits
449 );
450
451VOID
452EFIAPI
453ArmCallSEV (
454 VOID
455 );
456
457VOID
458EFIAPI
459ArmCallWFE (
460 VOID
461 );
462
463VOID
464EFIAPI
465ArmCallWFI (
466
467 VOID
468 );
469
470UINTN
471EFIAPI
472ArmReadMpidr (
473 VOID
474 );
475
476UINTN
477EFIAPI
478ArmReadMidr (
479 VOID
480 );
481
482UINT32
483EFIAPI
484ArmReadCpacr (
485 VOID
486 );
487
488VOID
489EFIAPI
490ArmWriteCpacr (
491 IN UINT32 Access
492 );
493
494VOID
495EFIAPI
496ArmEnableVFP (
497 VOID
498 );
499
500UINT32
501EFIAPI
502ArmReadSctlr (
503 VOID
504 );
505
506VOID
507EFIAPI
508ArmWriteSctlr (
509 IN UINT32 Value
510 );
511
512UINTN
513EFIAPI
514ArmReadHVBar (
515 VOID
516 );
517
518VOID
519EFIAPI
520ArmWriteHVBar (
521 IN UINTN HypModeVectorBase
522 );
523
524//
525// Helper functions for accessing CPU ACTLR
526//
527
528UINTN
529EFIAPI
530ArmReadCpuActlr (
531 VOID
532 );
533
534VOID
535EFIAPI
536ArmWriteCpuActlr (
537 IN UINTN Val
538 );
539
540VOID
541EFIAPI
542ArmSetCpuActlrBit (
543 IN UINTN Bits
544 );
545
546VOID
547EFIAPI
548ArmUnsetCpuActlrBit (
549 IN UINTN Bits
550 );
551
552//
553// Accessors for the architected generic timer registers
554//
555
556#define ARM_ARCH_TIMER_ENABLE (1 << 0)
557#define ARM_ARCH_TIMER_IMASK (1 << 1)
558#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
559
560UINTN
561EFIAPI
562ArmReadCntFrq (
563 VOID
564 );
565
566VOID
567EFIAPI
568ArmWriteCntFrq (
569 UINTN FreqInHz
570 );
571
572UINT64
573EFIAPI
574ArmReadCntPct (
575 VOID
576 );
577
578UINTN
579EFIAPI
580ArmReadCntkCtl (
581 VOID
582 );
583
584VOID
585EFIAPI
586ArmWriteCntkCtl (
587 UINTN Val
588 );
589
590UINTN
591EFIAPI
592ArmReadCntpTval (
593 VOID
594 );
595
596VOID
597EFIAPI
598ArmWriteCntpTval (
599 UINTN Val
600 );
601
602UINTN
603EFIAPI
604ArmReadCntpCtl (
605 VOID
606 );
607
608VOID
609EFIAPI
610ArmWriteCntpCtl (
611 UINTN Val
612 );
613
614UINTN
615EFIAPI
616ArmReadCntvTval (
617 VOID
618 );
619
620VOID
621EFIAPI
622ArmWriteCntvTval (
623 UINTN Val
624 );
625
626UINTN
627EFIAPI
628ArmReadCntvCtl (
629 VOID
630 );
631
632VOID
633EFIAPI
634ArmWriteCntvCtl (
635 UINTN Val
636 );
637
638UINT64
639EFIAPI
640ArmReadCntvCt (
641 VOID
642 );
643
644UINT64
645EFIAPI
646ArmReadCntpCval (
647 VOID
648 );
649
650VOID
651EFIAPI
652ArmWriteCntpCval (
653 UINT64 Val
654 );
655
656UINT64
657EFIAPI
658ArmReadCntvCval (
659 VOID
660 );
661
662VOID
663EFIAPI
664ArmWriteCntvCval (
665 UINT64 Val
666 );
667
668UINT64
669EFIAPI
670ArmReadCntvOff (
671 VOID
672 );
673
674VOID
675EFIAPI
676ArmWriteCntvOff (
677 UINT64 Val
678 );
679
680UINTN
681EFIAPI
682ArmGetPhysicalAddressBits (
683 VOID
684 );
685
689
696BOOLEAN
697EFIAPI
699 VOID
700 );
701
707BOOLEAN
708EFIAPI
710 VOID
711 );
712
713#ifdef MDE_CPU_AARCH64
717
724BOOLEAN
725EFIAPI
726ArmHasVhe (
727 VOID
728 );
729
736BOOLEAN
737EFIAPI
739 VOID
740 );
741
748BOOLEAN
749EFIAPI
750ArmHasEte (
751 VOID
752 );
753
754#endif // MDE_CPU_AARCH64
755
756#ifdef MDE_CPU_ARM
760
767BOOLEAN
768EFIAPI
770 VOID
771 );
772
773#endif // MDE_CPU_ARM
774
775#endif // ARM_LIB_H_
UINT64 UINTN
BOOLEAN EFIAPI ArmHasVhe(VOID)
Definition: AArch64Lib.c:61
BOOLEAN EFIAPI ArmHasTrbe(VOID)
Definition: AArch64Lib.c:76
BOOLEAN EFIAPI ArmHasEte(VOID)
Definition: AArch64Lib.c:91
UINT32 ReadCCSIDR2(IN UINT32 CSSELR)
BOOLEAN EFIAPI ArmHasGicSystemRegisters(VOID)
Definition: AArch64Lib.c:29
BOOLEAN EFIAPI ArmHasCcidx(VOID)
Definition: AArch64Lib.c:43
UINTN ReadCCSIDR(IN UINT32 CSSELR)
UINT32 ReadCLIDR(VOID)
VOID EFIAPI ArmInvalidateTlb(VOID)
BOOLEAN EFIAPI ArmHasSecurityExtensions(VOID)
Definition: ArmV7Lib.c:44
#define IN
Definition: Base.h:279
UINT64 EFI_PHYSICAL_ADDRESS
Definition: UefiBaseType.h:50
UINT64 EFI_VIRTUAL_ADDRESS
Definition: UefiBaseType.h:55