28CHAR16 *mPciHostBridgeAcpiAddressSpaceTypeStr[] = {
50 END_ENTIRE_DEVICE_PATH_SUBTYPE,
52 END_DEVICE_PATH_LENGTH,
59CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
60 L
"Mem", L
"I/O", L
"Bus"
88 IN UINT64 AllocationAttributes,
89 IN BOOLEAN DmaAbove4G,
90 IN BOOLEAN NoExtendedConfigSpace,
100 if ((Count ==
NULL) ||
103 (MemAbove4G ==
NULL) ||
105 (PMemAbove4G ==
NULL))
122 mRootBridge.
Bus.Base = BusMin;
123 mRootBridge.
Bus.Limit = BusMax;
124 mRootBridge.
Io.Base = Io->Base;
125 mRootBridge.
Io.Limit = Io->Limit;
126 mRootBridge.
Mem.Base = Mem->Base;
127 mRootBridge.
Mem.Limit = Mem->Limit;
128 mRootBridge.
MemAbove4G.Base = MemAbove4G->Base;
129 mRootBridge.
MemAbove4G.Limit = MemAbove4G->Limit;
130 mRootBridge.
PMem.Base = PMem->Base;
131 mRootBridge.
PMem.Limit = PMem->Limit;
133 mRootBridge.
PMemAbove4G.Limit = PMemAbove4G->Limit;
175 IN VOID *Configuration
179 UINTN RootBridgeIndex;
181 DEBUG ((DEBUG_ERROR,
"PciHostBridge: Resource conflict happens!\n"));
185 while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
186 DEBUG ((DEBUG_ERROR,
"RootBridge[%d]:\n", RootBridgeIndex++));
187 for ( ; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
189 Descriptor->ResType <
190 ARRAY_SIZE (mPciHostBridgeAcpiAddressSpaceTypeStr)
194 " %s: Length/Alignment = 0x%lx / 0x%lx\n",
195 mPciHostBridgeAcpiAddressSpaceTypeStr[Descriptor->ResType],
197 Descriptor->AddrRangeMax
199 if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
202 " Granularity/SpecificFlag = %ld / %02x%s\n",
203 Descriptor->AddrSpaceGranularity,
204 Descriptor->SpecificFlag,
205 ((Descriptor->SpecificFlag &
206 EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
207 ) != 0) ? L
" (Prefetchable)" : L
""
215 ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
PACKED struct @89 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
VOID EFIAPI PciHostBridgeUtilityFreeRootBridges(IN PCI_ROOT_BRIDGE *Bridges, IN UINTN Count)
PCI_ROOT_BRIDGE *EFIAPI PciHostBridgeUtilityGetRootBridges(OUT UINTN *Count, IN UINT64 Attributes, IN UINT64 AllocationAttributes, IN BOOLEAN DmaAbove4G, IN BOOLEAN NoExtendedConfigSpace, IN UINTN BusMin, IN UINTN BusMax, IN PCI_ROOT_BRIDGE_APERTURE *Io, IN PCI_ROOT_BRIDGE_APERTURE *Mem, IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, IN PCI_ROOT_BRIDGE_APERTURE *PMem, IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G)
VOID EFIAPI PciHostBridgeUtilityResourceConflict(IN VOID *Configuration)
#define ARRAY_SIZE(Array)
#define GLOBAL_REMOVE_IF_UNREFERENCED
#define DEBUG(Expression)
PCI_ROOT_BRIDGE_APERTURE Io
IO aperture which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE PMem
Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
BOOLEAN NoExtendedConfigSpace
UINT32 Segment
Segment number.
EFI_DEVICE_PATH_PROTOCOL * DevicePath
Device path.
PCI_ROOT_BRIDGE_APERTURE Mem
MMIO aperture below 4GB which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE PMemAbove4G
Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE MemAbove4G
MMIO aperture above 4GB which can be used by the root bridge.
PCI_ROOT_BRIDGE_APERTURE Bus
Bus aperture which can be used by the root bridge.
UINT64 AllocationAttributes