Data Structures
struct	IDE_REGS_BASE_ADDR

struct	_PEI_ATA_CONTROLLER_PPI

Macros
#define	PEI_ATA_CONTROLLER_PPI_GUID

#define	PEI_ICH_IDE_NONE 0x00

#define	PEI_ICH_IDE_PRIMARY 0x01

#define	PEI_ICH_IDE_SECONDARY 0x02

#define	PEI_ICH_SATA_NONE 0x04

#define	PEI_ICH_SATA_PRIMARY 0x08

#define	PEI_ICH_SATA_SECONDARY 0x010

Typedefs
typedef struct _PEI_ATA_CONTROLLER_PPI	PEI_ATA_CONTROLLER_PPI

typedef EFI_STATUS(EFIAPI *	PEI_ENABLE_ATA) (IN EFI_PEI_SERVICES *PeiServices, IN PEI_ATA_CONTROLLER_PPI This, IN UINT8 ChannelMask)

typedef UINT32(EFIAPI *	GET_IDE_REGS_BASE_ADDR) (IN EFI_PEI_SERVICES *PeiServices, IN PEI_ATA_CONTROLLER_PPI This, OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr)

Variables
EFI_GUID	gPeiAtaControllerPpiGuid

Detailed Description

Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve the base I/O port address for each of the enabled IDE and SATA channels.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file AtaController.h.

Macro Definition Documentation

◆ PEI_ATA_CONTROLLER_PPI_GUID

#define PEI_ATA_CONTROLLER_PPI_GUID

Value:

  { \
    0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \
  }

Global ID for the PEI_ATA_CONTROLLER_PPI.

Definition at line 17 of file AtaController.h.

◆ PEI_ICH_IDE_NONE

#define PEI_ICH_IDE_NONE 0x00

This bit is used in the ChannelMask parameter of EnableAtaChannel() to disable the IDE channels. This is designed for old generation chipset with PATA/SATA controllers. It may be ignored in PPI implementation for new generation chipset without PATA controller.

Definition at line 33 of file AtaController.h.

◆ PEI_ICH_IDE_PRIMARY

#define PEI_ICH_IDE_PRIMARY 0x01

This bit is used in the ChannelMask parameter of EnableAtaChannel() to enable the Primary IDE channel. This is designed for old generation chipset with PATA/SATA controllers. It may be ignored in PPI implementation for new generation chipset without PATA controller.

Definition at line 41 of file AtaController.h.

◆ PEI_ICH_IDE_SECONDARY

#define PEI_ICH_IDE_SECONDARY 0x02

This bit is used in the ChannelMask parameter of EnableAtaChannel() to enable the Secondary IDE channel. This is designed for old generation chipset with PATA/SATA controllers. It may be ignored in PPI implementation for new generation chipset without PATA controller.

Definition at line 49 of file AtaController.h.

◆ PEI_ICH_SATA_NONE

#define PEI_ICH_SATA_NONE 0x04

This bit is used in the ChannelMask parameter of EnableAtaChannel() to disable the SATA channel. This is designed for old generation chipset with PATA/SATA controllers. It may be ignored in PPI implementation for new generation chipset without PATA controller.

Definition at line 57 of file AtaController.h.

◆ PEI_ICH_SATA_PRIMARY

#define PEI_ICH_SATA_PRIMARY 0x08

This bit is used in the ChannelMask parameter of EnableAtaChannel() to enable the Primary SATA channel. This is designed for old generation chipset with PATA/SATA controllers. It may be ignored in PPI implementation for new generation chipset without PATA controller.

Definition at line 65 of file AtaController.h.

◆ PEI_ICH_SATA_SECONDARY

#define PEI_ICH_SATA_SECONDARY 0x010

This bit is used in the ChannelMask parameter of EnableAtaChannel() to enable the Secondary SATA channel. This is designed for old generation chipset with PATA/SATA controllers. It may be ignored in PPI implementation for new generation chipset without PATA controller.

Definition at line 73 of file AtaController.h.

Typedef Documentation

◆ GET_IDE_REGS_BASE_ADDR

typedef UINT32(EFIAPI * GET_IDE_REGS_BASE_ADDR) (IN EFI_PEI_SERVICES **PeiServices, IN PEI_ATA_CONTROLLER_PPI *This, OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr)

Retrieves the I/O port base addresses for command and control registers of the enabled IDE/SATA channels.

This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O port base addresses for the command and control registers of the IDE and SATA channels that were previously enabled in EnableAtaChannel(). The number of enabled IDE and SATA channels is returned.

Parameters

[in]	PeiServices	The pointer to the PEI Services Table.
[in]	This	The pointer to this instance of the PEI_ATA_CONTROLLER_PPI.
[out]	IdeRegsBaseAddr	The pointer to caller allocated space to return the I/O port base addresses of the IDE and SATA channels that were previosuly enabled with EnableAtaChannel().

Returns: The number of enabled IDE and SATA channels in the platform.

Definition at line 135 of file AtaController.h.

◆ PEI_ATA_CONTROLLER_PPI

typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI

Forward declaration for the PEI_ATA_CONTROLLER_PPI.

Definition at line 25 of file AtaController.h.

◆ PEI_ENABLE_ATA

typedef EFI_STATUS(EFIAPI * PEI_ENABLE_ATA) (IN EFI_PEI_SERVICES **PeiServices, IN PEI_ATA_CONTROLLER_PPI *This, IN UINT8 ChannelMask)

Sets IDE and SATA channels to an enabled or disabled state.

This service enables or disables the IDE and SATA channels specified by ChannelMask. It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy. The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function.

If the new state is set, then EFI_SUCCESS is returned. If the new state can not be set, then EFI_DEVICE_ERROR is returned.