11#ifndef _PEI_ATA_CONTROLLER_PPI_H_
12#define _PEI_ATA_CONTROLLER_PPI_H_
17#define PEI_ATA_CONTROLLER_PPI_GUID \
19 0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \
33#define PEI_ICH_IDE_NONE 0x00
41#define PEI_ICH_IDE_PRIMARY 0x01
49#define PEI_ICH_IDE_SECONDARY 0x02
57#define PEI_ICH_SATA_NONE 0x04
65#define PEI_ICH_SATA_PRIMARY 0x08
73#define PEI_ICH_SATA_SECONDARY 0x010
151extern EFI_GUID gPeiAtaControllerPpiGuid;
UINT32(EFIAPI * GET_IDE_REGS_BASE_ADDR)(IN EFI_PEI_SERVICES **PeiServices, IN PEI_ATA_CONTROLLER_PPI *This, OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr)
EFI_STATUS(EFIAPI * PEI_ENABLE_ATA)(IN EFI_PEI_SERVICES **PeiServices, IN PEI_ATA_CONTROLLER_PPI *This, IN UINT8 ChannelMask)
UINT16 CommandBlockBaseAddr
UINT16 ControlBlockBaseAddr