AtomMsr.h

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#ifndef __ATOM_MSR_H__
#define __ATOM_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x1C || \
    DisplayModel == 0x26 || \
    DisplayModel == 0x27 || \
    DisplayModel == 0x35 || \
    DisplayModel == 0x36    \
    )                       \
   )
 
#define MSR_ATOM_PLATFORM_ID  0x00000017
 
typedef union {
  struct {
    UINT32    Reserved1             : 8;
    UINT32    MaximumQualifiedRatio : 5;
    UINT32    Reserved2             : 19;
    UINT32    Reserved3             : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_ATOM_PLATFORM_ID_REGISTER;
 
#define MSR_ATOM_EBL_CR_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    Reserved1                   : 1;
    UINT32    DataErrorCheckingEnable     : 1;
    UINT32    ResponseErrorCheckingEnable : 1;
    UINT32    AERR_DriveEnable            : 1;
    UINT32    BERR_Enable                 : 1;
    UINT32    Reserved2                   : 1;
    UINT32    Reserved3                   : 1;
    UINT32    BINIT_DriverEnable          : 1;
    UINT32    Reserved4                   : 1;
    UINT32    ExecuteBIST                 : 1;
    UINT32    AERR_ObservationEnabled     : 1;
    UINT32    Reserved5                   : 1;
    UINT32    BINIT_ObservationEnabled    : 1;
    UINT32    Reserved6                   : 1;
    UINT32    ResetVector                 : 1;
    UINT32    Reserved7                   : 1;
    UINT32    APICClusterID               : 2;
    UINT32    Reserved8                   : 2;
    UINT32    SymmetricArbitrationID      : 2;
    UINT32    IntegerBusFrequencyRatio    : 5;
    UINT32    Reserved9                   : 5;
    UINT32    Reserved10                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_ATOM_EBL_CR_POWERON_REGISTER;
 
#define MSR_ATOM_LASTBRANCH_0_FROM_IP  0x00000040
#define MSR_ATOM_LASTBRANCH_1_FROM_IP  0x00000041
#define MSR_ATOM_LASTBRANCH_2_FROM_IP  0x00000042
#define MSR_ATOM_LASTBRANCH_3_FROM_IP  0x00000043
#define MSR_ATOM_LASTBRANCH_4_FROM_IP  0x00000044
#define MSR_ATOM_LASTBRANCH_5_FROM_IP  0x00000045
#define MSR_ATOM_LASTBRANCH_6_FROM_IP  0x00000046
#define MSR_ATOM_LASTBRANCH_7_FROM_IP  0x00000047
 
#define MSR_ATOM_LASTBRANCH_0_TO_IP  0x00000060
#define MSR_ATOM_LASTBRANCH_1_TO_IP  0x00000061
#define MSR_ATOM_LASTBRANCH_2_TO_IP  0x00000062
#define MSR_ATOM_LASTBRANCH_3_TO_IP  0x00000063
#define MSR_ATOM_LASTBRANCH_4_TO_IP  0x00000064
#define MSR_ATOM_LASTBRANCH_5_TO_IP  0x00000065
#define MSR_ATOM_LASTBRANCH_6_TO_IP  0x00000066
#define MSR_ATOM_LASTBRANCH_7_TO_IP  0x00000067
 
#define MSR_ATOM_FSB_FREQ  0x000000CD
 
typedef union {
  struct {
    UINT32    ScalableBusSpeed : 3;
    UINT32    Reserved1        : 29;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_ATOM_FSB_FREQ_REGISTER;
 
#define MSR_ATOM_BBL_CR_CTL3  0x0000011E
 
typedef union {
  struct {
    UINT32    L2HardwareEnabled : 1;
    UINT32    Reserved1         : 7;
    UINT32    L2Enabled         : 1;
    UINT32    Reserved2         : 14;
    UINT32    L2NotPresent      : 1;
    UINT32    Reserved3         : 8;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_ATOM_BBL_CR_CTL3_REGISTER;
 
#define MSR_ATOM_PERF_STATUS  0x00000198
 
typedef union {
  struct {
    UINT32    CurrentPerformanceStateValue : 16;
    UINT32    Reserved1                    : 16;
    UINT32    Reserved2                    : 8;
    UINT32    MaximumBusRatio              : 5;
    UINT32    Reserved3                    : 19;
  } Bits;
  UINT64    Uint64;
} MSR_ATOM_PERF_STATUS_REGISTER;
 
#define MSR_ATOM_THERM2_CTL  0x0000019D
 
typedef union {
  struct {
    UINT32    Reserved1 : 16;
    UINT32    TM_SELECT : 1;
    UINT32    Reserved2 : 15;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_ATOM_THERM2_CTL_REGISTER;
 
#define MSR_ATOM_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings                    : 1;
    UINT32    Reserved1                      : 2;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 1;
    UINT32    Reserved4                      : 1;
    UINT32    FERR                           : 1;
    UINT32    BTS                            : 1;
    UINT32    PEBS                           : 1;
    UINT32    TM2       : 1;
    UINT32    Reserved5 : 2;
    UINT32    EIST      : 1;
    UINT32    Reserved6 : 1;
    UINT32    MONITOR   : 1;
    UINT32    Reserved7 : 1;
    UINT32    EISTLock             : 1;
    UINT32    Reserved8            : 1;
    UINT32    LimitCpuidMaxval     : 1;
    UINT32    xTPR_Message_Disable : 1;
    UINT32    Reserved9            : 8;
    UINT32    Reserved10           : 2;
    UINT32    XD                   : 1;
    UINT32    Reserved11           : 29;
  } Bits;
  UINT64    Uint64;
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_ATOM_LASTBRANCH_TOS  0x000001C9
 
#define MSR_ATOM_LER_FROM_LIP  0x000001DD
 
#define MSR_ATOM_LER_TO_LIP  0x000001DE
 
#define MSR_ATOM_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_ATOM_PEBS_ENABLE_REGISTER;
 
#define MSR_ATOM_PKG_C2_RESIDENCY  0x000003F8
 
#define MSR_ATOM_PKG_C4_RESIDENCY  0x000003F9
 
#define MSR_ATOM_PKG_C6_RESIDENCY  0x000003FA
 
#endif