TianoCore EDK2 master
AtomMsr.h
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1
18#ifndef __ATOM_MSR_H__
19#define __ATOM_MSR_H__
20
22
32#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x1C || \
36 DisplayModel == 0x26 || \
37 DisplayModel == 0x27 || \
38 DisplayModel == 0x35 || \
39 DisplayModel == 0x36 \
40 ) \
41 )
42
60#define MSR_ATOM_PLATFORM_ID 0x00000017
61
65typedef union {
69 struct {
70 UINT32 Reserved1 : 8;
75 UINT32 Reserved2 : 19;
76 UINT32 Reserved3 : 32;
77 } Bits;
81 UINT32 Uint32;
85 UINT64 Uint64;
87
107#define MSR_ATOM_EBL_CR_POWERON 0x0000002A
108
112typedef union {
116 struct {
117 UINT32 Reserved1 : 1;
136 UINT32 BERR_Enable : 1;
137 UINT32 Reserved2 : 1;
138 UINT32 Reserved3 : 1;
143 UINT32 Reserved4 : 1;
147 UINT32 ExecuteBIST : 1;
153 UINT32 Reserved5 : 1;
159 UINT32 Reserved6 : 1;
163 UINT32 ResetVector : 1;
164 UINT32 Reserved7 : 1;
168 UINT32 APICClusterID : 2;
169 UINT32 Reserved8 : 2;
178 UINT32 Reserved9 : 5;
179 UINT32 Reserved10 : 32;
180 } Bits;
184 UINT32 Uint32;
188 UINT64 Uint64;
190
218#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
219#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
220#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
221#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
222#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
223#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
224#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
225#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
227
254#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
255#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
256#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
257#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
258#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
259#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
260#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
261#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
263
282#define MSR_ATOM_FSB_FREQ 0x000000CD
283
287typedef union {
291 struct {
309 UINT32 Reserved1 : 29;
310 UINT32 Reserved2 : 32;
311 } Bits;
315 UINT32 Uint32;
319 UINT64 Uint64;
321
340#define MSR_ATOM_BBL_CR_CTL3 0x0000011E
341
345typedef union {
349 struct {
355 UINT32 Reserved1 : 7;
361 UINT32 L2Enabled : 1;
362 UINT32 Reserved2 : 14;
366 UINT32 L2NotPresent : 1;
367 UINT32 Reserved3 : 8;
368 UINT32 Reserved4 : 32;
369 } Bits;
373 UINT32 Uint32;
377 UINT64 Uint64;
379
398#define MSR_ATOM_PERF_STATUS 0x00000198
399
403typedef union {
407 struct {
412 UINT32 Reserved1 : 16;
413 UINT32 Reserved2 : 8;
418 UINT32 MaximumBusRatio : 5;
419 UINT32 Reserved3 : 19;
420 } Bits;
424 UINT64 Uint64;
426
445#define MSR_ATOM_THERM2_CTL 0x0000019D
446
450typedef union {
454 struct {
455 UINT32 Reserved1 : 16;
463 UINT32 TM_SELECT : 1;
464 UINT32 Reserved2 : 15;
465 UINT32 Reserved3 : 32;
466 } Bits;
470 UINT32 Uint32;
474 UINT64 Uint64;
476
496#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
497
501typedef union {
505 struct {
509 UINT32 FastStrings : 1;
510 UINT32 Reserved1 : 2;
516 UINT32 Reserved2 : 3;
521 UINT32 Reserved3 : 1;
522 UINT32 Reserved4 : 1;
529 UINT32 FERR : 1;
533 UINT32 BTS : 1;
538 UINT32 PEBS : 1;
553 UINT32 TM2 : 1;
554 UINT32 Reserved5 : 2;
559 UINT32 EIST : 1;
560 UINT32 Reserved6 : 1;
564 UINT32 MONITOR : 1;
565 UINT32 Reserved7 : 1;
574 UINT32 EISTLock : 1;
575 UINT32 Reserved8 : 1;
584 UINT32 Reserved9 : 8;
585 UINT32 Reserved10 : 2;
589 UINT32 XD : 1;
590 UINT32 Reserved11 : 29;
591 } Bits;
595 UINT64 Uint64;
597
616#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
617
635#define MSR_ATOM_LER_FROM_LIP 0x000001DD
636
655#define MSR_ATOM_LER_TO_LIP 0x000001DE
656
676#define MSR_ATOM_PEBS_ENABLE 0x000003F1
677
681typedef union {
685 struct {
689 UINT32 Enable : 1;
690 UINT32 Reserved1 : 31;
691 UINT32 Reserved2 : 32;
692 } Bits;
696 UINT32 Uint32;
700 UINT64 Uint64;
702
723#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
724
745#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
746
767#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA
768
769#endif