- Generated on Fri Nov 15 2024 18:01:36 for TianoCore EDK2 by
1.9.6
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TianoCore EDK2 master
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#include <Register/Intel/ArchitecturalMsr.h>Go to the source code of this file.
Data Structures | |
| union | MSR_ATOM_PLATFORM_ID_REGISTER |
| union | MSR_ATOM_EBL_CR_POWERON_REGISTER |
| union | MSR_ATOM_FSB_FREQ_REGISTER |
| union | MSR_ATOM_BBL_CR_CTL3_REGISTER |
| union | MSR_ATOM_PERF_STATUS_REGISTER |
| union | MSR_ATOM_THERM2_CTL_REGISTER |
| union | MSR_ATOM_IA32_MISC_ENABLE_REGISTER |
| union | MSR_ATOM_PEBS_ENABLE_REGISTER |
MSR Definitions for the Intel(R) Atom(TM) Processor Family.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
Definition in file AtomMsr.h.
| #define IS_ATOM_PROCESSOR | ( | DisplayFamily, | |
| DisplayModel | |||
| ) |
Is Intel(R) Atom(TM) Processor Family?
| DisplayFamily | Display Family ID |
| DisplayModel | Display Model ID |
| TRUE | Yes, it is. |
| FALSE | No, it isn't. |
| #define MSR_ATOM_BBL_CR_CTL3 0x0000011E |
Shared.
| ECX | MSR_ATOM_BBL_CR_CTL3 (0x0000011E) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER. |
Example usage
| #define MSR_ATOM_EBL_CR_POWERON 0x0000002A |
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
| ECX | MSR_ATOM_EBL_CR_POWERON (0x0000002A) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER. |
Example usage
| #define MSR_ATOM_FSB_FREQ 0x000000CD |
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable bus clock speed for processors based on Intel Atom microarchitecture:.
| ECX | MSR_ATOM_FSB_FREQ (0x000000CD) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_FSB_FREQ_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_FSB_FREQ_REGISTER. |
Example usage
| #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0 |
Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.
| ECX | MSR_ATOM_IA32_MISC_ENABLE (0x000001A0) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER. |
Example usage
| #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040 |
Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction . See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.
| ECX | MSR_ATOM_LASTBRANCH_n_FROM_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060 |
Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains pointers to the destination instruction.
| ECX | MSR_ATOM_LASTBRANCH_n_TO_IP |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9 |
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H).
| ECX | MSR_ATOM_LASTBRANCH_TOS (0x000001C9) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_LER_FROM_LIP 0x000001DD |
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.
| ECX | MSR_ATOM_LER_FROM_LIP (0x000001DD) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_LER_TO_LIP 0x000001DE |
Unique. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.
| ECX | MSR_ATOM_LER_TO_LIP (0x000001DE) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_PEBS_ENABLE 0x000003F1 |
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling (PEBS).".
| ECX | MSR_ATOM_PEBS_ENABLE (0x000003F1) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER. |
Example usage
| #define MSR_ATOM_PERF_STATUS 0x00000198 |
Shared.
| ECX | MSR_ATOM_PERF_STATUS (0x00000198) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_PERF_STATUS_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_PERF_STATUS_REGISTER. |
Example usage
| #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8 |
Package. Package C2 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package. Package C2 Residency Counter. (R/O) Time that this package is in processor-specific C2 states since last reset. Counts at 1 Mhz frequency.
| ECX | MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9 |
Package. Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package. Package C4 Residency Counter. (R/O) Time that this package is in processor-specific C4 states since last reset. Counts at 1 Mhz frequency.
| ECX | MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA |
Package. Package C6 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States. Package. Package C6 Residency Counter. (R/O) Time that this package is in processor-specific C6 states since last reset. Counts at 1 Mhz frequency.
| ECX | MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_ATOM_PLATFORM_ID 0x00000017 |
Shared. Model Specific Platform ID (R).
| ECX | MSR_ATOM_PLATFORM_ID (0x00000017) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_PLATFORM_ID_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_PLATFORM_ID_REGISTER. |
Example usage
| #define MSR_ATOM_THERM2_CTL 0x0000019D |
Shared.
| ECX | MSR_ATOM_THERM2_CTL (0x0000019D) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_ATOM_THERM2_CTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_ATOM_THERM2_CTL_REGISTER. |
Example usage
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