TianoCore EDK2 master
Core2Msr.h
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1
18#ifndef __CORE2_MSR_H__
19#define __CORE2_MSR_H__
20
22
32#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x0F || \
36 DisplayModel == 0x17 \
37 ) \
38 )
39
57#define MSR_CORE2_PLATFORM_ID 0x00000017
58
62typedef union {
66 struct {
67 UINT32 Reserved1 : 8;
72 UINT32 Reserved2 : 19;
73 UINT32 Reserved3 : 18;
77 UINT32 PlatformId : 3;
78 UINT32 Reserved4 : 11;
79 } Bits;
83 UINT64 Uint64;
85
105#define MSR_CORE2_EBL_CR_POWERON 0x0000002A
106
110typedef union {
114 struct {
115 UINT32 Reserved1 : 1;
136 UINT32 Reserved2 : 1;
137 UINT32 Reserved3 : 1;
150 UINT32 ExecuteBIST : 1;
163 UINT32 Reserved4 : 1;
167 UINT32 ResetVector : 1;
168 UINT32 Reserved5 : 1;
172 UINT32 APICClusterID : 2;
178 UINT32 Reserved6 : 1;
187 UINT32 Reserved7 : 5;
188 UINT32 Reserved8 : 32;
189 } Bits;
193 UINT32 Uint32;
197 UINT64 Uint64;
199
218#define MSR_CORE2_FEATURE_CONTROL 0x0000003A
219
223typedef union {
227 struct {
228 UINT32 Reserved1 : 3;
234 UINT32 SMRREnable : 1;
235 UINT32 Reserved2 : 28;
236 UINT32 Reserved3 : 32;
237 } Bits;
241 UINT32 Uint32;
245 UINT64 Uint64;
247
271#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
272#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
273#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
274#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
276
299#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
300#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
301#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
302#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
304
325#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
326
330typedef union {
334 struct {
335 UINT32 Reserved1 : 12;
339 UINT32 PhysBase : 20;
340 UINT32 Reserved2 : 32;
341 } Bits;
345 UINT32 Uint32;
349 UINT64 Uint64;
351
372#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
373
377typedef union {
381 struct {
382 UINT32 Reserved1 : 11;
386 UINT32 Valid : 1;
390 UINT32 PhysMask : 20;
391 UINT32 Reserved2 : 32;
392 } Bits;
396 UINT32 Uint32;
400 UINT64 Uint64;
402
421#define MSR_CORE2_FSB_FREQ 0x000000CD
422
426typedef union {
430 struct {
448 UINT32 Reserved1 : 29;
449 UINT32 Reserved2 : 32;
450 } Bits;
454 UINT32 Uint32;
458 UINT64 Uint64;
460
479#define MSR_CORE2_PERF_STATUS 0x00000198
480
484typedef union {
488 struct {
493 UINT32 Reserved1 : 15;
498 UINT32 XEOperation : 1;
499 UINT32 Reserved2 : 8;
504 UINT32 MaximumBusRatio : 5;
505 UINT32 Reserved3 : 1;
512 UINT32 Reserved4 : 17;
513 } Bits;
517 UINT64 Uint64;
519
538#define MSR_CORE2_THERM2_CTL 0x0000019D
539
543typedef union {
547 struct {
548 UINT32 Reserved1 : 16;
556 UINT32 TM_SELECT : 1;
557 UINT32 Reserved2 : 15;
558 UINT32 Reserved3 : 32;
559 } Bits;
563 UINT32 Uint32;
567 UINT64 Uint64;
569
589#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
590
594typedef union {
598 struct {
602 UINT32 FastStrings : 1;
603 UINT32 Reserved1 : 2;
609 UINT32 Reserved2 : 3;
614 UINT32 Reserved3 : 1;
628 UINT32 FERR : 1;
632 UINT32 BTS : 1;
637 UINT32 PEBS : 1;
652 UINT32 TM2 : 1;
653 UINT32 Reserved4 : 2;
658 UINT32 EIST : 1;
659 UINT32 Reserved5 : 1;
663 UINT32 MONITOR : 1;
683 UINT32 EISTLock : 1;
684 UINT32 Reserved6 : 1;
693 UINT32 Reserved7 : 8;
694 UINT32 Reserved8 : 2;
698 UINT32 XD : 1;
699 UINT32 Reserved9 : 2;
720 UINT32 IDADisable : 1;
730 UINT32 Reserved10 : 24;
731 } Bits;
735 UINT64 Uint64;
737
756#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
757
775#define MSR_CORE2_LER_FROM_LIP 0x000001DD
776
795#define MSR_CORE2_LER_TO_LIP 0x000001DE
796
816#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
817#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
818#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
820
840#define MSR_CORE2_PERF_CAPABILITIES 0x00000345
841
845typedef union {
849 struct {
853 UINT32 LBR_FMT : 6;
857 UINT32 PEBS_FMT : 1;
861 UINT32 PEBS_ARCH_REG : 1;
862 UINT32 Reserved1 : 24;
863 UINT32 Reserved2 : 32;
864 } Bits;
868 UINT32 Uint32;
872 UINT64 Uint64;
874
891#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
892
909#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E
910
927#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
928
945#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
946
966#define MSR_CORE2_PEBS_ENABLE 0x000003F1
967
971typedef union {
975 struct {
979 UINT32 Enable : 1;
980 UINT32 Reserved1 : 31;
981 UINT32 Reserved2 : 32;
982 } Bits;
986 UINT32 Uint32;
990 UINT64 Uint64;
992
1018#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
1019#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
1020#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
1021#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
1022#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
1023#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
1024#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
1025#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
1027
1045#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8
1046
1047#endif