Core2Msr.h

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#ifndef __CORE2_MSR_H__
#define __CORE2_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   (                        \
    DisplayModel == 0x0F || \
    DisplayModel == 0x17    \
    )                       \
   )
 
#define MSR_CORE2_PLATFORM_ID  0x00000017
 
typedef union {
  struct {
    UINT32    Reserved1             : 8;
    UINT32    MaximumQualifiedRatio : 5;
    UINT32    Reserved2             : 19;
    UINT32    Reserved3             : 18;
    UINT32    PlatformId            : 3;
    UINT32    Reserved4             : 11;
  } Bits;
  UINT64    Uint64;
} MSR_CORE2_PLATFORM_ID_REGISTER;
 
#define MSR_CORE2_EBL_CR_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    Reserved1                   : 1;
    UINT32    DataErrorCheckingEnable     : 1;
    UINT32    ResponseErrorCheckingEnable : 1;
    UINT32    MCERR_DriveEnable           : 1;
    UINT32    AddressParityEnable         : 1;
    UINT32    Reserved2                   : 1;
    UINT32    Reserved3                   : 1;
    UINT32    BINIT_DriverEnable          : 1;
    UINT32    OutputTriStateEnable        : 1;
    UINT32    ExecuteBIST                 : 1;
    UINT32    MCERR_ObservationEnabled    : 1;
    UINT32    IntelTXTCapableChipset      : 1;
    UINT32    BINIT_ObservationEnabled    : 1;
    UINT32    Reserved4                   : 1;
    UINT32    ResetVector                 : 1;
    UINT32    Reserved5                   : 1;
    UINT32    APICClusterID               : 2;
    UINT32    NonIntegerBusRatio          : 1;
    UINT32    Reserved6                   : 1;
    UINT32    SymmetricArbitrationID      : 2;
    UINT32    IntegerBusFrequencyRatio    : 5;
    UINT32    Reserved7                   : 5;
    UINT32    Reserved8                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_EBL_CR_POWERON_REGISTER;
 
#define MSR_CORE2_FEATURE_CONTROL  0x0000003A
 
typedef union {
  struct {
    UINT32    Reserved1  : 3;
    UINT32    SMRREnable : 1;
    UINT32    Reserved2  : 28;
    UINT32    Reserved3  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_FEATURE_CONTROL_REGISTER;
 
#define MSR_CORE2_LASTBRANCH_0_FROM_IP  0x00000040
#define MSR_CORE2_LASTBRANCH_1_FROM_IP  0x00000041
#define MSR_CORE2_LASTBRANCH_2_FROM_IP  0x00000042
#define MSR_CORE2_LASTBRANCH_3_FROM_IP  0x00000043
 
#define MSR_CORE2_LASTBRANCH_0_TO_IP  0x00000060
#define MSR_CORE2_LASTBRANCH_1_TO_IP  0x00000061
#define MSR_CORE2_LASTBRANCH_2_TO_IP  0x00000062
#define MSR_CORE2_LASTBRANCH_3_TO_IP  0x00000063
 
#define MSR_CORE2_SMRR_PHYSBASE  0x000000A0
 
typedef union {
  struct {
    UINT32    Reserved1 : 12;
    UINT32    PhysBase  : 20;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_SMRR_PHYSBASE_REGISTER;
 
#define MSR_CORE2_SMRR_PHYSMASK  0x000000A1
 
typedef union {
  struct {
    UINT32    Reserved1 : 11;
    UINT32    Valid     : 1;
    UINT32    PhysMask  : 20;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_SMRR_PHYSMASK_REGISTER;
 
#define MSR_CORE2_FSB_FREQ  0x000000CD
 
typedef union {
  struct {
    UINT32    ScalableBusSpeed : 3;
    UINT32    Reserved1        : 29;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_FSB_FREQ_REGISTER;
 
#define MSR_CORE2_PERF_STATUS  0x00000198
 
typedef union {
  struct {
    UINT32    CurrentPerformanceStateValue : 16;
    UINT32    Reserved1                    : 15;
    UINT32    XEOperation                  : 1;
    UINT32    Reserved2                    : 8;
    UINT32    MaximumBusRatio              : 5;
    UINT32    Reserved3                    : 1;
    UINT32    NonIntegerBusRatio           : 1;
    UINT32    Reserved4                    : 17;
  } Bits;
  UINT64    Uint64;
} MSR_CORE2_PERF_STATUS_REGISTER;
 
#define MSR_CORE2_THERM2_CTL  0x0000019D
 
typedef union {
  struct {
    UINT32    Reserved1 : 16;
    UINT32    TM_SELECT : 1;
    UINT32    Reserved2 : 15;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_THERM2_CTL_REGISTER;
 
#define MSR_CORE2_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings                    : 1;
    UINT32    Reserved1                      : 2;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 1;
    UINT32    HardwarePrefetcherDisable      : 1;
    UINT32    FERR                           : 1;
    UINT32    BTS                            : 1;
    UINT32    PEBS                           : 1;
    UINT32    TM2       : 1;
    UINT32    Reserved4 : 2;
    UINT32    EIST      : 1;
    UINT32    Reserved5 : 1;
    UINT32    MONITOR   : 1;
    UINT32    AdjacentCacheLinePrefetchDisable : 1;
    UINT32    EISTLock             : 1;
    UINT32    Reserved6            : 1;
    UINT32    LimitCpuidMaxval     : 1;
    UINT32    xTPR_Message_Disable : 1;
    UINT32    Reserved7            : 8;
    UINT32    Reserved8            : 2;
    UINT32    XD                   : 1;
    UINT32    Reserved9            : 2;
    UINT32    DCUPrefetcherDisable : 1;
    UINT32    IDADisable : 1;
    UINT32    IPPrefetcherDisable : 1;
    UINT32    Reserved10          : 24;
  } Bits;
  UINT64    Uint64;
} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_CORE2_LASTBRANCH_TOS  0x000001C9
 
#define MSR_CORE2_LER_FROM_LIP  0x000001DD
 
#define MSR_CORE2_LER_TO_LIP  0x000001DE
 
#define MSR_CORE2_PERF_FIXED_CTR0  0x00000309
#define MSR_CORE2_PERF_FIXED_CTR1  0x0000030A
#define MSR_CORE2_PERF_FIXED_CTR2  0x0000030B
 
#define MSR_CORE2_PERF_CAPABILITIES  0x00000345
 
typedef union {
  struct {
    UINT32    LBR_FMT       : 6;
    UINT32    PEBS_FMT      : 1;
    UINT32    PEBS_ARCH_REG : 1;
    UINT32    Reserved1     : 24;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_PERF_CAPABILITIES_REGISTER;
 
#define MSR_CORE2_PERF_FIXED_CTR_CTRL  0x0000038D
 
#define MSR_CORE2_PERF_GLOBAL_STATUS  0x0000038E
 
#define MSR_CORE2_PERF_GLOBAL_CTRL  0x0000038F
 
#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL  0x00000390
 
#define MSR_CORE2_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE2_PEBS_ENABLE_REGISTER;
 
#define MSR_CORE2_EMON_L3_CTR_CTL0  0x000107CC
#define MSR_CORE2_EMON_L3_CTR_CTL1  0x000107CD
#define MSR_CORE2_EMON_L3_CTR_CTL2  0x000107CE
#define MSR_CORE2_EMON_L3_CTR_CTL3  0x000107CF
#define MSR_CORE2_EMON_L3_CTR_CTL4  0x000107D0
#define MSR_CORE2_EMON_L3_CTR_CTL5  0x000107D1
#define MSR_CORE2_EMON_L3_CTR_CTL6  0x000107D2
#define MSR_CORE2_EMON_L3_CTR_CTL7  0x000107D3
 
#define MSR_CORE2_EMON_L3_GL_CTL  0x000107D8
 
#endif