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Core2Msr.h File Reference

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Data Structures

union  MSR_CORE2_PLATFORM_ID_REGISTER
 
union  MSR_CORE2_EBL_CR_POWERON_REGISTER
 
union  MSR_CORE2_FEATURE_CONTROL_REGISTER
 
union  MSR_CORE2_SMRR_PHYSBASE_REGISTER
 
union  MSR_CORE2_SMRR_PHYSMASK_REGISTER
 
union  MSR_CORE2_FSB_FREQ_REGISTER
 
union  MSR_CORE2_PERF_STATUS_REGISTER
 
union  MSR_CORE2_THERM2_CTL_REGISTER
 
union  MSR_CORE2_IA32_MISC_ENABLE_REGISTER
 
union  MSR_CORE2_PERF_CAPABILITIES_REGISTER
 
union  MSR_CORE2_PEBS_ENABLE_REGISTER
 

Macros

#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel)
 
#define MSR_CORE2_PLATFORM_ID   0x00000017
 
#define MSR_CORE2_EBL_CR_POWERON   0x0000002A
 
#define MSR_CORE2_FEATURE_CONTROL   0x0000003A
 
#define MSR_CORE2_SMRR_PHYSBASE   0x000000A0
 
#define MSR_CORE2_SMRR_PHYSMASK   0x000000A1
 
#define MSR_CORE2_FSB_FREQ   0x000000CD
 
#define MSR_CORE2_PERF_STATUS   0x00000198
 
#define MSR_CORE2_THERM2_CTL   0x0000019D
 
#define MSR_CORE2_IA32_MISC_ENABLE   0x000001A0
 
#define MSR_CORE2_LASTBRANCH_TOS   0x000001C9
 
#define MSR_CORE2_LER_FROM_LIP   0x000001DD
 
#define MSR_CORE2_LER_TO_LIP   0x000001DE
 
#define MSR_CORE2_PERF_CAPABILITIES   0x00000345
 
#define MSR_CORE2_PERF_FIXED_CTR_CTRL   0x0000038D
 
#define MSR_CORE2_PERF_GLOBAL_STATUS   0x0000038E
 
#define MSR_CORE2_PERF_GLOBAL_CTRL   0x0000038F
 
#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL   0x00000390
 
#define MSR_CORE2_PEBS_ENABLE   0x000003F1
 
#define MSR_CORE2_EMON_L3_GL_CTL   0x000107D8
 
#define MSR_CORE2_LASTBRANCH_0_FROM_IP   0x00000040
 
#define MSR_CORE2_LASTBRANCH_1_FROM_IP   0x00000041
 
#define MSR_CORE2_LASTBRANCH_2_FROM_IP   0x00000042
 
#define MSR_CORE2_LASTBRANCH_3_FROM_IP   0x00000043
 
#define MSR_CORE2_LASTBRANCH_0_TO_IP   0x00000060
 
#define MSR_CORE2_LASTBRANCH_1_TO_IP   0x00000061
 
#define MSR_CORE2_LASTBRANCH_2_TO_IP   0x00000062
 
#define MSR_CORE2_LASTBRANCH_3_TO_IP   0x00000063
 
#define MSR_CORE2_PERF_FIXED_CTR0   0x00000309
 
#define MSR_CORE2_PERF_FIXED_CTR1   0x0000030A
 
#define MSR_CORE2_PERF_FIXED_CTR2   0x0000030B
 
#define MSR_CORE2_EMON_L3_CTR_CTL0   0x000107CC
 
#define MSR_CORE2_EMON_L3_CTR_CTL1   0x000107CD
 
#define MSR_CORE2_EMON_L3_CTR_CTL2   0x000107CE
 
#define MSR_CORE2_EMON_L3_CTR_CTL3   0x000107CF
 
#define MSR_CORE2_EMON_L3_CTR_CTL4   0x000107D0
 
#define MSR_CORE2_EMON_L3_CTR_CTL5   0x000107D1
 
#define MSR_CORE2_EMON_L3_CTR_CTL6   0x000107D2
 
#define MSR_CORE2_EMON_L3_CTR_CTL7   0x000107D3
 

Detailed Description

MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Definition in file Core2Msr.h.

Macro Definition Documentation

◆ IS_CORE2_PROCESSOR

#define IS_CORE2_PROCESSOR (   DisplayFamily,
  DisplayModel 
)
Value:
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x0F || \
DisplayModel == 0x17 \
) \
)

Is Intel(R) Core(TM) 2 Processor Family?

Parameters
DisplayFamilyDisplay Family ID
DisplayModelDisplay Model ID
Return values
TRUEYes, it is.
FALSENo, it isn't.

Definition at line 32 of file Core2Msr.h.

◆ MSR_CORE2_EBL_CR_POWERON

#define MSR_CORE2_EBL_CR_POWERON   0x0000002A

Shared. Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

Parameters
ECXMSR_CORE2_EBL_CR_POWERON (0x0000002A)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.

Example usage

#define MSR_CORE2_EBL_CR_POWERON
Definition: Core2Msr.h:105
UINT64 EFIAPI AsmReadMsr64(IN UINT32 Index)
Definition: GccInlinePriv.c:60
UINT64 EFIAPI AsmWriteMsr64(IN UINT32 Index, IN UINT64 Value)
Note
MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.

Definition at line 105 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL0

#define MSR_CORE2_EMON_L3_CTR_CTL0   0x000107CC

Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.

Parameters
ECXMSR_CORE2_EMON_L3_CTR_CTLn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_EMON_L3_CTR_CTL0
Definition: Core2Msr.h:1018
Note
MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM. MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM. MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM. MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM. MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM. MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM. MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM. MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.

Definition at line 1018 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL1

#define MSR_CORE2_EMON_L3_CTR_CTL1   0x000107CD

Definition at line 1019 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL2

#define MSR_CORE2_EMON_L3_CTR_CTL2   0x000107CE

Definition at line 1020 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL3

#define MSR_CORE2_EMON_L3_CTR_CTL3   0x000107CF

Definition at line 1021 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL4

#define MSR_CORE2_EMON_L3_CTR_CTL4   0x000107D0

Definition at line 1022 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL5

#define MSR_CORE2_EMON_L3_CTR_CTL5   0x000107D1

Definition at line 1023 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL6

#define MSR_CORE2_EMON_L3_CTR_CTL6   0x000107D2

Definition at line 1024 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_CTR_CTL7

#define MSR_CORE2_EMON_L3_CTR_CTL7   0x000107D3

Definition at line 1025 of file Core2Msr.h.

◆ MSR_CORE2_EMON_L3_GL_CTL

#define MSR_CORE2_EMON_L3_GL_CTL   0x000107D8

Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.

Parameters
ECXMSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_EMON_L3_GL_CTL
Definition: Core2Msr.h:1045
Note
MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.

Definition at line 1045 of file Core2Msr.h.

◆ MSR_CORE2_FEATURE_CONTROL

#define MSR_CORE2_FEATURE_CONTROL   0x0000003A

Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.

Parameters
ECXMSR_CORE2_FEATURE_CONTROL (0x0000003A)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.

Example usage

Note
MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.

Definition at line 218 of file Core2Msr.h.

◆ MSR_CORE2_FSB_FREQ

#define MSR_CORE2_FSB_FREQ   0x000000CD

Shared. Scalable Bus Speed(RO) This field indicates the intended scalable bus clock speed for processors based on Intel Core microarchitecture:.

Parameters
ECXMSR_CORE2_FSB_FREQ (0x000000CD)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_FSB_FREQ_REGISTER.

Example usage

Note
MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.

Definition at line 421 of file Core2Msr.h.

◆ MSR_CORE2_IA32_MISC_ENABLE

#define MSR_CORE2_IA32_MISC_ENABLE   0x000001A0

Enable Misc. Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.

Parameters
ECXMSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.

Example usage

Note
MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.

Definition at line 589 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_0_FROM_IP

#define MSR_CORE2_LASTBRANCH_0_FROM_IP   0x00000040

Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains pointers to the source instruction. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.5.

Parameters
ECXMSR_CORE2_LASTBRANCH_n_FROM_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.

Definition at line 271 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_0_TO_IP

#define MSR_CORE2_LASTBRANCH_0_TO_IP   0x00000060

Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch record registers on the last branch record stack. This To_IP part of the stack contains pointers to the destination instruction.

Parameters
ECXMSR_CORE2_LASTBRANCH_n_TO_IP
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_LASTBRANCH_0_TO_IP
Definition: Core2Msr.h:299
Note
MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.

Definition at line 299 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_1_FROM_IP

#define MSR_CORE2_LASTBRANCH_1_FROM_IP   0x00000041

Definition at line 272 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_1_TO_IP

#define MSR_CORE2_LASTBRANCH_1_TO_IP   0x00000061

Definition at line 300 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_2_FROM_IP

#define MSR_CORE2_LASTBRANCH_2_FROM_IP   0x00000042

Definition at line 273 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_2_TO_IP

#define MSR_CORE2_LASTBRANCH_2_TO_IP   0x00000062

Definition at line 301 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_3_FROM_IP

#define MSR_CORE2_LASTBRANCH_3_FROM_IP   0x00000043

Definition at line 274 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_3_TO_IP

#define MSR_CORE2_LASTBRANCH_3_TO_IP   0x00000063

Definition at line 302 of file Core2Msr.h.

◆ MSR_CORE2_LASTBRANCH_TOS

#define MSR_CORE2_LASTBRANCH_TOS   0x000001C9

Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H).

Parameters
ECXMSR_CORE2_LASTBRANCH_TOS (0x000001C9)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_LASTBRANCH_TOS
Definition: Core2Msr.h:756
Note
MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.

Definition at line 756 of file Core2Msr.h.

◆ MSR_CORE2_LER_FROM_LIP

#define MSR_CORE2_LER_FROM_LIP   0x000001DD

Unique. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters
ECXMSR_CORE2_LER_FROM_LIP (0x000001DD)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_LER_FROM_LIP
Definition: Core2Msr.h:775
Note
MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.

Definition at line 775 of file Core2Msr.h.

◆ MSR_CORE2_LER_TO_LIP

#define MSR_CORE2_LER_TO_LIP   0x000001DE

Unique. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.

Parameters
ECXMSR_CORE2_LER_TO_LIP (0x000001DE)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_LER_TO_LIP
Definition: Core2Msr.h:795
Note
MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.

Definition at line 795 of file Core2Msr.h.

◆ MSR_CORE2_PEBS_ENABLE

#define MSR_CORE2_PEBS_ENABLE   0x000003F1

Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling (PEBS).".

Parameters
ECXMSR_CORE2_PEBS_ENABLE (0x000003F1)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.

Example usage

Note
MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.

Definition at line 966 of file Core2Msr.h.

◆ MSR_CORE2_PERF_CAPABILITIES

#define MSR_CORE2_PERF_CAPABILITIES   0x00000345

Unique. RO. This applies to processors that do not support architectural perfmon version 2.

Parameters
ECXMSR_CORE2_PERF_CAPABILITIES (0x00000345)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.

Example usage

Note
MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.

Definition at line 840 of file Core2Msr.h.

◆ MSR_CORE2_PERF_FIXED_CTR0

#define MSR_CORE2_PERF_FIXED_CTR0   0x00000309

Unique. Fixed-Function Performance Counter Register n (R/W).

Parameters
ECXMSR_CORE2_PERF_FIXED_CTRn
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_PERF_FIXED_CTR0
Definition: Core2Msr.h:816
Note
MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM. MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM. MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.

Definition at line 816 of file Core2Msr.h.

◆ MSR_CORE2_PERF_FIXED_CTR1

#define MSR_CORE2_PERF_FIXED_CTR1   0x0000030A

Definition at line 817 of file Core2Msr.h.

◆ MSR_CORE2_PERF_FIXED_CTR2

#define MSR_CORE2_PERF_FIXED_CTR2   0x0000030B

Definition at line 818 of file Core2Msr.h.

◆ MSR_CORE2_PERF_FIXED_CTR_CTRL

#define MSR_CORE2_PERF_FIXED_CTR_CTRL   0x0000038D

Unique. Fixed-Function-Counter Control Register (R/W).

Parameters
ECXMSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.

Definition at line 891 of file Core2Msr.h.

◆ MSR_CORE2_PERF_GLOBAL_CTRL

#define MSR_CORE2_PERF_GLOBAL_CTRL   0x0000038F

Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".

Parameters
ECXMSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_PERF_GLOBAL_CTRL
Definition: Core2Msr.h:927
Note
MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.

Definition at line 927 of file Core2Msr.h.

◆ MSR_CORE2_PERF_GLOBAL_OVF_CTRL

#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL   0x00000390

Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".

Parameters
ECXMSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

Note
MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.

Definition at line 945 of file Core2Msr.h.

◆ MSR_CORE2_PERF_GLOBAL_STATUS

#define MSR_CORE2_PERF_GLOBAL_STATUS   0x0000038E

Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".

Parameters
ECXMSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
EAXLower 32-bits of MSR value.
EDXUpper 32-bits of MSR value.

Example usage

UINT64 Msr;
#define MSR_CORE2_PERF_GLOBAL_STATUS
Definition: Core2Msr.h:909
Note
MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.

Definition at line 909 of file Core2Msr.h.

◆ MSR_CORE2_PERF_STATUS

#define MSR_CORE2_PERF_STATUS   0x00000198

Shared.

Parameters
ECXMSR_CORE2_PERF_STATUS (0x00000198)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_PERF_STATUS_REGISTER.

Example usage

Note
MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.

Definition at line 479 of file Core2Msr.h.

◆ MSR_CORE2_PLATFORM_ID

#define MSR_CORE2_PLATFORM_ID   0x00000017

Shared. Model Specific Platform ID (R).

Parameters
ECXMSR_CORE2_PLATFORM_ID (0x00000017)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.

Example usage

Note
MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.

Definition at line 57 of file Core2Msr.h.

◆ MSR_CORE2_SMRR_PHYSBASE

#define MSR_CORE2_SMRR_PHYSBASE   0x000000A0

Unique. System Management Mode Base Address register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM.

Parameters
ECXMSR_CORE2_SMRR_PHYSBASE (0x000000A0)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.

Example usage

Note
MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.

Definition at line 325 of file Core2Msr.h.

◆ MSR_CORE2_SMRR_PHYSMASK

#define MSR_CORE2_SMRR_PHYSMASK   0x000000A1

Unique. System Management Mode Physical Address Mask register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM.

Parameters
ECXMSR_CORE2_SMRR_PHYSMASK (0x000000A1)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.

Example usage

Note
MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.

Definition at line 372 of file Core2Msr.h.

◆ MSR_CORE2_THERM2_CTL

#define MSR_CORE2_THERM2_CTL   0x0000019D

Unique.

Parameters
ECXMSR_CORE2_THERM2_CTL (0x0000019D)
EAXLower 32-bits of MSR value. Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
EDXUpper 32-bits of MSR value. Described by the type MSR_CORE2_THERM2_CTL_REGISTER.

Example usage

Note
MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.

Definition at line 538 of file Core2Msr.h.