CoreMsr.h

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#ifndef __CORE_MSR_H__
#define __CORE_MSR_H__
 
#include <Register/Intel/ArchitecturalMsr.h>
 
#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
  (DisplayFamily == 0x06 && \
   ( \
    DisplayModel == 0x0E \
    ) \
   )
 
#define MSR_CORE_P5_MC_ADDR  0x00000000
 
#define MSR_CORE_P5_MC_TYPE  0x00000001
 
#define MSR_CORE_EBL_CR_POWERON  0x0000002A
 
typedef union {
  struct {
    UINT32    Reserved1                   : 1;
    UINT32    DataErrorCheckingEnable     : 1;
    UINT32    ResponseErrorCheckingEnable : 1;
    UINT32    MCERR_DriveEnable           : 1;
    UINT32    AddressParityEnable         : 1;
    UINT32    Reserved2                   : 2;
    UINT32    BINIT_DriverEnable          : 1;
    UINT32    OutputTriStateEnable        : 1;
    UINT32    ExecuteBIST                 : 1;
    UINT32    MCERR_ObservationEnabled    : 1;
    UINT32    Reserved3                   : 1;
    UINT32    BINIT_ObservationEnabled    : 1;
    UINT32    Reserved4                   : 1;
    UINT32    ResetVector                 : 1;
    UINT32    Reserved5                   : 1;
    UINT32    APICClusterID               : 2;
    UINT32    SystemBusFrequency          : 1;
    UINT32    Reserved6                   : 1;
    UINT32    SymmetricArbitrationID      : 2;
    UINT32    ClockFrequencyRatio         : 5;
    UINT32    Reserved7                   : 5;
    UINT32    Reserved8                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE_EBL_CR_POWERON_REGISTER;
 
#define MSR_CORE_LASTBRANCH_0  0x00000040
#define MSR_CORE_LASTBRANCH_1  0x00000041
#define MSR_CORE_LASTBRANCH_2  0x00000042
#define MSR_CORE_LASTBRANCH_3  0x00000043
#define MSR_CORE_LASTBRANCH_4  0x00000044
#define MSR_CORE_LASTBRANCH_5  0x00000045
#define MSR_CORE_LASTBRANCH_6  0x00000046
#define MSR_CORE_LASTBRANCH_7  0x00000047
 
#define MSR_CORE_FSB_FREQ  0x000000CD
 
typedef union {
  struct {
    UINT32    ScalableBusSpeed : 3;
    UINT32    Reserved1        : 29;
    UINT32    Reserved2        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE_FSB_FREQ_REGISTER;
 
#define MSR_CORE_BBL_CR_CTL3  0x0000011E
 
typedef union {
  struct {
    UINT32    L2HardwareEnabled : 1;
    UINT32    Reserved1         : 7;
    UINT32    L2Enabled         : 1;
    UINT32    Reserved2         : 14;
    UINT32    L2NotPresent      : 1;
    UINT32    Reserved3         : 8;
    UINT32    Reserved4         : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE_BBL_CR_CTL3_REGISTER;
 
#define MSR_CORE_THERM2_CTL  0x0000019D
 
typedef union {
  struct {
    UINT32    Reserved1 : 16;
    UINT32    TM_SELECT : 1;
    UINT32    Reserved2 : 15;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE_THERM2_CTL_REGISTER;
 
#define MSR_CORE_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    Reserved1                      : 3;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 2;
    UINT32    FERR                           : 1;
    UINT32    BTS                            : 1;
    UINT32    Reserved4                      : 1;
    UINT32    TM2              : 1;
    UINT32    Reserved5        : 2;
    UINT32    EIST             : 1;
    UINT32    Reserved6        : 1;
    UINT32    MONITOR          : 1;
    UINT32    Reserved7        : 1;
    UINT32    Reserved8        : 2;
    UINT32    LimitCpuidMaxval : 1;
    UINT32    Reserved9        : 9;
    UINT32    Reserved10       : 2;
    UINT32    XD               : 1;
    UINT32    Reserved11       : 29;
  } Bits;
  UINT64    Uint64;
} MSR_CORE_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_CORE_LASTBRANCH_TOS  0x000001C9
 
#define MSR_CORE_LER_FROM_LIP  0x000001DD
 
#define MSR_CORE_LER_TO_LIP  0x000001DE
 
#define MSR_CORE_MTRRPHYSBASE0  0x00000200
#define MSR_CORE_MTRRPHYSBASE1  0x00000202
#define MSR_CORE_MTRRPHYSBASE2  0x00000204
#define MSR_CORE_MTRRPHYSBASE3  0x00000206
#define MSR_CORE_MTRRPHYSBASE4  0x00000208
#define MSR_CORE_MTRRPHYSBASE5  0x0000020A
#define MSR_CORE_MTRRPHYSMASK6  0x0000020D
#define MSR_CORE_MTRRPHYSMASK7  0x0000020F
 
#define MSR_CORE_MTRRPHYSMASK0  0x00000201
#define MSR_CORE_MTRRPHYSMASK1  0x00000203
#define MSR_CORE_MTRRPHYSMASK2  0x00000205
#define MSR_CORE_MTRRPHYSMASK3  0x00000207
#define MSR_CORE_MTRRPHYSMASK4  0x00000209
#define MSR_CORE_MTRRPHYSMASK5  0x0000020B
#define MSR_CORE_MTRRPHYSBASE6  0x0000020C
#define MSR_CORE_MTRRPHYSBASE7  0x0000020E
 
#define MSR_CORE_MTRRFIX64K_00000  0x00000250
 
#define MSR_CORE_MTRRFIX16K_80000  0x00000258
 
#define MSR_CORE_MTRRFIX16K_A0000  0x00000259
 
#define MSR_CORE_MTRRFIX4K_C0000  0x00000268
 
#define MSR_CORE_MTRRFIX4K_C8000  0x00000269
 
#define MSR_CORE_MTRRFIX4K_D0000  0x0000026A
 
#define MSR_CORE_MTRRFIX4K_D8000  0x0000026B
 
#define MSR_CORE_MTRRFIX4K_E0000  0x0000026C
 
#define MSR_CORE_MTRRFIX4K_E8000  0x0000026D
 
#define MSR_CORE_MTRRFIX4K_F0000  0x0000026E
 
#define MSR_CORE_MTRRFIX4K_F8000  0x0000026F
 
#define MSR_CORE_MC4_CTL  0x0000040C
 
#define MSR_CORE_MC4_STATUS  0x0000040D
 
#define MSR_CORE_MC4_ADDR  0x0000040E
 
#define MSR_CORE_MC3_ADDR  0x00000412
 
#define MSR_CORE_MC3_MISC  0x00000413
 
#define MSR_CORE_MC5_CTL  0x00000414
 
#define MSR_CORE_MC5_STATUS  0x00000415
 
#define MSR_CORE_MC5_ADDR  0x00000416
 
#define MSR_CORE_MC5_MISC  0x00000417
 
#define MSR_CORE_IA32_EFER  0xC0000080
 
typedef union {
  struct {
    UINT32    Reserved1 : 11;
    UINT32    NXE       : 1;
    UINT32    Reserved2 : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_CORE_IA32_EFER_REGISTER;
 
#endif