- Generated on Fri Nov 15 2024 18:01:36 for TianoCore EDK2 by
1.9.6
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TianoCore EDK2 master
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#include <Register/Intel/ArchitecturalMsr.h>Go to the source code of this file.
Data Structures | |
| union | MSR_CORE_EBL_CR_POWERON_REGISTER |
| union | MSR_CORE_FSB_FREQ_REGISTER |
| union | MSR_CORE_BBL_CR_CTL3_REGISTER |
| union | MSR_CORE_THERM2_CTL_REGISTER |
| union | MSR_CORE_IA32_MISC_ENABLE_REGISTER |
| union | MSR_CORE_IA32_EFER_REGISTER |
MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
Definition in file CoreMsr.h.
| #define IS_CORE_PROCESSOR | ( | DisplayFamily, | |
| DisplayModel | |||
| ) |
| #define MSR_CORE_BBL_CR_CTL3 0x0000011E |
Shared.
| ECX | MSR_CORE_BBL_CR_CTL3 (0x0000011E) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER. |
Example usage
| #define MSR_CORE_EBL_CR_POWERON 0x0000002A |
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
| ECX | MSR_CORE_EBL_CR_POWERON (0x0000002A) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER. |
Example usage
| #define MSR_CORE_FSB_FREQ 0x000000CD |
Shared. Scalable Bus Speed (RO) This field indicates the scalable bus clock speed:.
| ECX | MSR_CORE_FSB_FREQ (0x000000CD) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_CORE_FSB_FREQ_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_CORE_FSB_FREQ_REGISTER. |
Example usage
| #define MSR_CORE_IA32_EFER 0xC0000080 |
Unique. See Table 2-2.
| ECX | MSR_CORE_IA32_EFER (0xC0000080) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_CORE_IA32_EFER_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_CORE_IA32_EFER_REGISTER. |
Example usage
| #define MSR_CORE_IA32_MISC_ENABLE 0x000001A0 |
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor functions to be enabled and disabled.
| ECX | MSR_CORE_IA32_MISC_ENABLE (0x000001A0) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER. |
Example usage
| #define MSR_CORE_LASTBRANCH_0 0x00000040 |
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
| ECX | MSR_CORE_LASTBRANCH_n |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_LASTBRANCH_TOS 0x000001C9 |
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See MSR_LASTBRANCH_0_FROM_IP (at 40H).
| ECX | MSR_CORE_LASTBRANCH_TOS (0x000001C9) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_LER_FROM_LIP 0x000001DD |
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.
| ECX | MSR_CORE_LER_FROM_LIP (0x000001DD) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_LER_TO_LIP 0x000001DE |
Unique. Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled.
| ECX | MSR_CORE_LER_TO_LIP (0x000001DE) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC3_ADDR 0x00000412 |
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
| ECX | MSR_CORE_MC3_ADDR (0x00000412) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC3_MISC 0x00000413 |
Unique.
| ECX | MSR_CORE_MC3_MISC (0x00000413) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC4_ADDR 0x0000040E |
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
| ECX | MSR_CORE_MC4_ADDR (0x0000040E) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC4_CTL 0x0000040C |
Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
| ECX | MSR_CORE_MC4_CTL (0x0000040C) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC4_STATUS 0x0000040D |
Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
| ECX | MSR_CORE_MC4_STATUS (0x0000040D) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC5_ADDR 0x00000416 |
Unique.
| ECX | MSR_CORE_MC5_ADDR (0x00000416) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC5_CTL 0x00000414 |
Unique.
| ECX | MSR_CORE_MC5_CTL (0x00000414) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC5_MISC 0x00000417 |
Unique.
| ECX | MSR_CORE_MC5_MISC (0x00000417) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MC5_STATUS 0x00000415 |
Unique.
| ECX | MSR_CORE_MC5_STATUS (0x00000415) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX16K_80000 0x00000258 |
Unique.
| ECX | MSR_CORE_MTRRFIX16K_80000 (0x00000258) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX16K_A0000 0x00000259 |
Unique.
| ECX | MSR_CORE_MTRRFIX16K_A0000 (0x00000259) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_C0000 0x00000268 |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_C0000 (0x00000268) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_C8000 0x00000269 |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_C8000 (0x00000269) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_D0000 0x0000026A |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_D0000 (0x0000026A) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_D8000 0x0000026B |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_D8000 (0x0000026B) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_E0000 0x0000026C |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_E0000 (0x0000026C) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_E8000 0x0000026D |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_E8000 (0x0000026D) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_F0000 0x0000026E |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_F0000 (0x0000026E) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX4K_F8000 0x0000026F |
Unique.
| ECX | MSR_CORE_MTRRFIX4K_F8000 (0x0000026F) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRFIX64K_00000 0x00000250 |
Unique.
| ECX | MSR_CORE_MTRRFIX64K_00000 (0x00000250) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRPHYSBASE0 0x00000200 |
Unique.
| ECX | MSR_CORE_MTRRPHYSBASEn |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_MTRRPHYSMASK0 0x00000201 |
Unique.
| ECX | MSR_CORE_MTRRPHYSMASKn (0x00000201) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_P5_MC_ADDR 0x00000000 |
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
| ECX | MSR_CORE_P5_MC_ADDR (0x00000000) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_P5_MC_TYPE 0x00000001 |
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
| ECX | MSR_CORE_P5_MC_TYPE (0x00000001) |
| EAX | Lower 32-bits of MSR value. |
| EDX | Upper 32-bits of MSR value. |
Example usage
| #define MSR_CORE_THERM2_CTL 0x0000019D |
Unique.
| ECX | MSR_CORE_THERM2_CTL (0x0000019D) |
| EAX | Lower 32-bits of MSR value. Described by the type MSR_CORE_THERM2_CTL_REGISTER. |
| EDX | Upper 32-bits of MSR value. Described by the type MSR_CORE_THERM2_CTL_REGISTER. |
Example usage
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