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EarlyFdtSerialPortLib16550.c
Go to the documentation of this file.
1
10#include <Base.h>
11#include <Library/BaseLib.h>
13#include <Library/IoLib.h>
14#include <Library/PcdLib.h>
16
17//
18// PCI Defintions.
19//
20#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
21
22//
23// 16550 UART register offsets and bitfields
24//
25#define R_UART_RXBUF 0 // LCR_DLAB = 0
26#define R_UART_TXBUF 0 // LCR_DLAB = 0
27#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
28#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
29#define R_UART_IER 1 // LCR_DLAB = 0
30#define R_UART_FCR 2
31#define B_UART_FCR_FIFOE BIT0
32#define B_UART_FCR_FIFO64 BIT5
33#define R_UART_LCR 3
34#define B_UART_LCR_DLAB BIT7
35#define R_UART_MCR 4
36#define B_UART_MCR_DTRC BIT0
37#define B_UART_MCR_RTS BIT1
38#define R_UART_LSR 5
39#define B_UART_LSR_RXRDY BIT0
40#define B_UART_LSR_TXRDY BIT5
41#define B_UART_LSR_TEMT BIT6
42#define R_UART_MSR 6
43#define B_UART_MSR_CTS BIT4
44#define B_UART_MSR_DSR BIT5
45#define B_UART_MSR_RI BIT6
46#define B_UART_MSR_DCD BIT7
47
61UINT8
63 UINTN Base,
64 UINTN Offset
65 )
66{
67 if (PcdGetBool (PcdSerialUseMmio)) {
68 if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
69 return (UINT8)MmioRead32 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
70 }
71
72 return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
73 } else {
74 return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
75 }
76}
77
92UINT8
94 UINTN Base,
95 UINTN Offset,
96 UINT8 Value
97 )
98{
99 if (PcdGetBool (PcdSerialUseMmio)) {
100 if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
101 return (UINT8)MmioWrite32 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), (UINT8)Value);
102 }
103
104 return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
105 } else {
106 return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
107 }
108}
109
118STATIC
119UINTN
121 VOID
122 )
123{
124 VOID *Base;
125 RETURN_STATUS Status;
126 UINT64 SerialConsoleAddress;
127
128 Base = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);
129 Status = FdtSerialGetConsolePort (Base, &SerialConsoleAddress);
130 if (RETURN_ERROR (Status)) {
131 return (UINTN)0;
132 }
133
134 return SerialConsoleAddress;
135}
136
145STATIC
146BOOLEAN
148 UINTN SerialRegisterBase
149 )
150{
151 if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
152 if (PcdGetBool (PcdSerialDetectCable)) {
153 //
154 // Wait for both DSR and CTS to be set
155 // DSR is set if a cable is connected.
156 // CTS is set if it is ok to transmit data
157 //
158 // DSR CTS Description Action
159 // === === ======================================== ========
160 // 0 0 No cable connected. Wait
161 // 0 1 No cable connected. Wait
162 // 1 0 Cable connected, but not clear to send. Wait
163 // 1 1 Cable connected, and clear to send. Transmit
164 //
165 return (BOOLEAN)((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
166 } else {
167 //
168 // Wait for both DSR and CTS to be set OR for DSR to be clear.
169 // DSR is set if a cable is connected.
170 // CTS is set if it is ok to transmit data
171 //
172 // DSR CTS Description Action
173 // === === ======================================== ========
174 // 0 0 No cable connected. Transmit
175 // 0 1 No cable connected. Transmit
176 // 1 0 Cable connected, but not clear to send. Wait
177 // 1 1 Cable connected, and clar to send. Transmit
178 //
179 return (BOOLEAN)((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
180 }
181 }
182
183 return TRUE;
184}
185
196RETURN_STATUS
197EFIAPI
199 VOID
200 )
201{
202 UINTN SerialRegisterBase;
203 UINT32 Divisor;
204 UINT32 CurrentDivisor;
205 BOOLEAN Initialized;
206
207 //
208 // Calculate divisor for baud generator
209 // Ref_Clk_Rate / Baud_Rate / 16
210 //
211 Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);
212 if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
213 Divisor++;
214 }
215
216 //
217 // Get the base address of the serial port in either I/O or MMIO space
218 //
219 SerialRegisterBase = GetSerialRegisterBase ();
220 if (SerialRegisterBase == 0) {
221 return RETURN_DEVICE_ERROR;
222 }
223
224 //
225 // See if the serial port is already initialized
226 //
227 Initialized = TRUE;
228 if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
229 Initialized = FALSE;
230 }
231
232 SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
233 CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
234 CurrentDivisor |= (UINT32)SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
235 SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
236 if (CurrentDivisor != Divisor) {
237 Initialized = FALSE;
238 }
239
240 if (Initialized) {
241 return RETURN_SUCCESS;
242 }
243
244 //
245 // Wait for the serial port to be ready.
246 // Verify that both the transmit FIFO and the shift register are empty.
247 //
248 while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
249 }
250
251 //
252 // Configure baud rate
253 //
254 SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
255 SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8)(Divisor >> 8));
256 SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8)(Divisor & 0xff));
257
258 //
259 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
260 // Strip reserved bits from PcdSerialLineControl
261 //
262 SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
263
264 //
265 // Enable and reset FIFOs
266 // Strip reserved bits from PcdSerialFifoControl
267 //
268 SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
269 SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
270
271 //
272 // Set FIFO Polled Mode by clearing IER after setting FCR
273 //
274 SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
275
276 //
277 // Put Modem Control Register(MCR) into its reset state of 0x00.
278 //
279 SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
280
281 return RETURN_SUCCESS;
282}
283
303UINTN
304EFIAPI
306 IN UINT8 *Buffer,
307 IN UINTN NumberOfBytes
308 )
309{
310 UINTN SerialRegisterBase;
311 UINTN Result;
312 UINTN Index;
313 UINTN FifoSize;
314
315 if (Buffer == NULL) {
316 return 0;
317 }
318
319 SerialRegisterBase = GetSerialRegisterBase ();
320 if (SerialRegisterBase == 0) {
321 return 0;
322 }
323
324 if (NumberOfBytes == 0) {
325 //
326 // Flush the hardware
327 //
328
329 //
330 // Wait for both the transmit FIFO and shift register empty.
331 //
332 while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
333 }
334
335 //
336 // Wait for the hardware flow control signal
337 //
338 while (!SerialPortWritable (SerialRegisterBase)) {
339 }
340
341 return 0;
342 }
343
344 //
345 // Compute the maximum size of the Tx FIFO
346 //
347 FifoSize = 1;
348 if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
349 if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
350 FifoSize = 16;
351 } else {
352 FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
353 }
354 }
355
356 Result = NumberOfBytes;
357 while (NumberOfBytes != 0) {
358 //
359 // Wait for the serial port to be ready, to make sure both the transmit FIFO
360 // and shift register empty.
361 //
362 while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
363 }
364
365 //
366 // Fill then entire Tx FIFO
367 //
368 for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
369 //
370 // Wait for the hardware flow control signal
371 //
372 while (!SerialPortWritable (SerialRegisterBase)) {
373 }
374
375 //
376 // Write byte to the transmit buffer.
377 //
378 SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
379 }
380 }
381
382 return Result;
383}
384
395UINTN
396EFIAPI
398 OUT UINT8 *Buffer,
399 IN UINTN NumberOfBytes
400 )
401{
402 UINTN SerialRegisterBase;
403 UINTN Result;
404 UINT8 Mcr;
405
406 if (NULL == Buffer) {
407 return 0;
408 }
409
410 SerialRegisterBase = GetSerialRegisterBase ();
411 if (SerialRegisterBase == 0) {
412 return 0;
413 }
414
415 Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
416
417 for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
418 //
419 // Wait for the serial port to have some data.
420 //
421 while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
422 if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
423 //
424 // Set RTS to let the peer send some data
425 //
426 SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
427 }
428 }
429
430 if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
431 //
432 // Clear RTS to prevent peer from sending data
433 //
434 SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
435 }
436
437 //
438 // Read byte from the receive buffer.
439 //
440 *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
441 }
442
443 return Result;
444}
445
456BOOLEAN
457EFIAPI
459 VOID
460 )
461{
462 UINTN SerialRegisterBase;
463
464 SerialRegisterBase = GetSerialRegisterBase ();
465 if (SerialRegisterBase == 0) {
466 return FALSE;
467 }
468
469 //
470 // Read the serial port status
471 //
472 if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
473 if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
474 //
475 // Clear RTS to prevent peer from sending data
476 //
477 SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
478 }
479
480 return TRUE;
481 }
482
483 if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
484 //
485 // Set RTS to let the peer send some data
486 //
487 SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
488 }
489
490 return FALSE;
491}
492
502RETURN_STATUS
503EFIAPI
505 IN UINT32 Control
506 )
507{
508 UINTN SerialRegisterBase;
509 UINT8 Mcr;
510
511 //
512 // First determine the parameter is invalid.
513 //
514 if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
515 EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0)
516 {
517 return RETURN_UNSUPPORTED;
518 }
519
520 SerialRegisterBase = GetSerialRegisterBase ();
521 if (SerialRegisterBase == 0) {
522 return RETURN_UNSUPPORTED;
523 }
524
525 //
526 // Read the Modem Control Register.
527 //
528 Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
529 Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
530
531 if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
532 Mcr |= B_UART_MCR_DTRC;
533 }
534
535 if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) {
536 Mcr |= B_UART_MCR_RTS;
537 }
538
539 //
540 // Write the Modem Control Register.
541 //
542 SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
543
544 return RETURN_SUCCESS;
545}
546
556RETURN_STATUS
557EFIAPI
559 OUT UINT32 *Control
560 )
561{
562 UINTN SerialRegisterBase;
563 UINT8 Msr;
564 UINT8 Mcr;
565 UINT8 Lsr;
566
567 SerialRegisterBase = GetSerialRegisterBase ();
568 if (SerialRegisterBase == 0) {
569 return RETURN_UNSUPPORTED;
570 }
571
572 *Control = 0;
573
574 //
575 // Read the Modem Status Register.
576 //
577 Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
578
579 if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
580 *Control |= EFI_SERIAL_CLEAR_TO_SEND;
581 }
582
583 if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
584 *Control |= EFI_SERIAL_DATA_SET_READY;
585 }
586
587 if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
588 *Control |= EFI_SERIAL_RING_INDICATE;
589 }
590
591 if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
592 *Control |= EFI_SERIAL_CARRIER_DETECT;
593 }
594
595 //
596 // Read the Modem Control Register.
597 //
598 Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
599
600 if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
601 *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
602 }
603
604 if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
605 *Control |= EFI_SERIAL_REQUEST_TO_SEND;
606 }
607
608 if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
609 *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
610 }
611
612 //
613 // Read the Line Status Register.
614 //
615 Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
616
617 if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
618 *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
619 }
620
621 if ((Lsr & B_UART_LSR_RXRDY) == 0) {
622 *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
623 }
624
625 return RETURN_SUCCESS;
626}
627
660RETURN_STATUS
661EFIAPI
663 IN OUT UINT64 *BaudRate,
664 IN OUT UINT32 *ReceiveFifoDepth,
665 IN OUT UINT32 *Timeout,
666 IN OUT EFI_PARITY_TYPE *Parity,
667 IN OUT UINT8 *DataBits,
668 IN OUT EFI_STOP_BITS_TYPE *StopBits
669 )
670{
671 UINTN SerialRegisterBase;
672 UINT32 SerialBaudRate;
673 UINTN Divisor;
674 UINT8 Lcr;
675 UINT8 LcrData;
676 UINT8 LcrParity;
677 UINT8 LcrStop;
678
679 SerialRegisterBase = GetSerialRegisterBase ();
680 if (SerialRegisterBase == 0) {
681 return RETURN_UNSUPPORTED;
682 }
683
684 //
685 // Check for default settings and fill in actual values.
686 //
687 if (*BaudRate == 0) {
688 *BaudRate = PcdGet32 (PcdSerialBaudRate);
689 }
690
691 SerialBaudRate = (UINT32)*BaudRate;
692
693 if (*DataBits == 0) {
694 LcrData = (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3);
695 *DataBits = LcrData + 5;
696 } else {
697 if ((*DataBits < 5) || (*DataBits > 8)) {
699 }
700
701 //
702 // Map 5..8 to 0..3
703 //
704 LcrData = (UINT8)(*DataBits - (UINT8)5);
705 }
706
707 if (*Parity == DefaultParity) {
708 LcrParity = (UINT8)((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
709 switch (LcrParity) {
710 case 0:
711 *Parity = NoParity;
712 break;
713
714 case 3:
715 *Parity = EvenParity;
716 break;
717
718 case 1:
719 *Parity = OddParity;
720 break;
721
722 case 7:
723 *Parity = SpaceParity;
724 break;
725
726 case 5:
727 *Parity = MarkParity;
728 break;
729
730 default:
731 break;
732 }
733 } else {
734 switch (*Parity) {
735 case NoParity:
736 LcrParity = 0;
737 break;
738
739 case EvenParity:
740 LcrParity = 3;
741 break;
742
743 case OddParity:
744 LcrParity = 1;
745 break;
746
747 case SpaceParity:
748 LcrParity = 7;
749 break;
750
751 case MarkParity:
752 LcrParity = 5;
753 break;
754
755 default:
757 }
758 }
759
760 if (*StopBits == DefaultStopBits) {
761 LcrStop = (UINT8)((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
762 switch (LcrStop) {
763 case 0:
764 *StopBits = OneStopBit;
765 break;
766
767 case 1:
768 if (*DataBits == 5) {
769 *StopBits = OneFiveStopBits;
770 } else {
771 *StopBits = TwoStopBits;
772 }
773
774 break;
775
776 default:
777 break;
778 }
779 } else {
780 switch (*StopBits) {
781 case OneStopBit:
782 LcrStop = 0;
783 break;
784
785 case OneFiveStopBits:
786 case TwoStopBits:
787 LcrStop = 1;
788 break;
789
790 default:
792 }
793 }
794
795 //
796 // Calculate divisor for baud generator
797 // Ref_Clk_Rate / Baud_Rate / 16
798 //
799 Divisor = PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16);
800 if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
801 Divisor++;
802 }
803
804 //
805 // Configure baud rate
806 //
807 SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
808 SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8)(Divisor >> 8));
809 SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8)(Divisor & 0xff));
810
811 //
812 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
813 // Strip reserved bits from line control value
814 //
815 Lcr = (UINT8)((LcrParity << 3) | (LcrStop << 2) | LcrData);
816 SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(Lcr & 0x3F));
817
818 return RETURN_SUCCESS;
819}
UINT64 UINTN
BOOLEAN EFIAPI SerialPortPoll(VOID)
STATIC UINT8 SerialPortWriteRegister(UINTN Base, UINTN Offset, UINT8 Value)
RETURN_STATUS EFIAPI SerialPortSetAttributes(IN OUT UINT64 *BaudRate, IN OUT UINT32 *ReceiveFifoDepth, IN OUT UINT32 *Timeout, IN OUT EFI_PARITY_TYPE *Parity, IN OUT UINT8 *DataBits, IN OUT EFI_STOP_BITS_TYPE *StopBits)
STATIC UINT8 SerialPortReadRegister(UINTN Base, UINTN Offset)
STATIC BOOLEAN SerialPortWritable(UINTN SerialRegisterBase)
UINTN EFIAPI SerialPortRead(OUT UINT8 *Buffer, IN UINTN NumberOfBytes)
RETURN_STATUS EFIAPI SerialPortInitialize(VOID)
RETURN_STATUS EFIAPI SerialPortSetControl(IN UINT32 Control)
STATIC UINTN GetSerialRegisterBase(VOID)
RETURN_STATUS EFIAPI SerialPortGetControl(OUT UINT32 *Control)
UINTN EFIAPI SerialPortWrite(IN UINT8 *Buffer, IN UINTN NumberOfBytes)
RETURN_STATUS EFIAPI FdtSerialGetConsolePort(IN CONST VOID *DeviceTree, OUT UINT64 *BaseAddress)
UINT8 EFIAPI IoWrite8(IN UINTN Port, IN UINT8 Value)
Definition: IoLibArmVirt.c:200
UINT8 EFIAPI MmioRead8(IN UINTN Address)
Definition: IoLib.c:82
UINT8 EFIAPI MmioWrite8(IN UINTN Address, IN UINT8 Value)
Definition: IoLib.c:126
UINT8 EFIAPI IoRead8(IN UINTN Port)
Definition: IoLibArmVirt.c:175
UINT32 EFIAPI MmioRead32(IN UINTN Address)
Definition: IoLib.c:262
UINT32 EFIAPI MmioWrite32(IN UINTN Address, IN UINT32 Value)
Definition: IoLib.c:309
#define NULL
Definition: Base.h:319
#define STATIC
Definition: Base.h:264
#define RETURN_ERROR(StatusCode)
Definition: Base.h:1061
#define RETURN_DEVICE_ERROR
Definition: Base.h:1104
#define RETURN_UNSUPPORTED
Definition: Base.h:1081
#define RETURN_SUCCESS
Definition: Base.h:1066
#define TRUE
Definition: Base.h:301
#define FALSE
Definition: Base.h:307
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
#define RETURN_INVALID_PARAMETER
Definition: Base.h:1076
#define PcdGet64(TokenName)
Definition: PcdLib.h:375
#define PcdGet8(TokenName)
Definition: PcdLib.h:336
#define PcdGet32(TokenName)
Definition: PcdLib.h:362
#define PcdGetBool(TokenName)
Definition: PcdLib.h:401
EFI_STOP_BITS_TYPE
Definition: SerialIo.h:53
EFI_PARITY_TYPE
Definition: SerialIo.h:41